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BranchCommit messageAuthorAge
feature/coreMinor refactor to regfile formal test moduleWarrick Lo4 weeks
feature/fuSync with 'master'Warrick Lo10 days
feature/shifterImplement slice-serial shifterWarrick Lo12 days
masterAdd DCO [skip ci]Warrick Lo3 weeks
 
 
AgeCommit messageAuthorFilesLines
12 daysImplement slice-serial shifterfeature/shifterWarrick Lo1-0/+109
2026-06-25Merge branch 'feature/fu' from MyDariellWarrick Lo5-39/+348
2026-06-22Clean up ALU before mergeMyDariell4-76/+24
2026-06-22Implement XOR, OR, AND logical operations in sliced ALUMyDariell2-3/+163
2026-06-21Implement ADD and SUB operations in sliced ALUMyDariell2-6/+207
2026-06-20Add basic ALU skeletonWarrick Lo2-0/+89
2026-06-20Minor refactor to regfile formal test modulefeature/coreWarrick Lo2-56/+83
2026-06-18Add formal verification for regfileWarrick Lo2-0/+244
2026-06-18Move typedefs to types.svh from montreal_pkgWarrick Lo4-13/+27
2026-06-17Sync with 'master'Warrick Lo60-87/+639
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