RV32E core for TinyTapeout, codename "Montréal". Mirror of https://github.com/ubc-asic/montreal.git. https://git.warricklo.net/montreal/atom?h=feature%2Ffu 2026-06-23T02:55:02+00:00 2026-06-23T02:55:02+00:00 MyDariell Dari3llsugiaman@gmail.com 2026-06-23T02:55:02+00:00 urn:sha1:7643e8f7afc960429dac33471dbcd56f1416a85f Co-authored-by: Warrick Lo <wlo@warricklo.net> Signed-off-by: Warrick Lo <wlo@warricklo.net> 2026-05-15T02:58:51+00:00 Chat 63841542+ChillZero@users.noreply.github.com 2026-05-15T02:58:51+00:00 urn:sha1:1fcb70209582fd05c03919b31502deb2b7af472a - simple_alu.sv: 32-bit ALU with add/sub, 33-bit extended overflow detection, and active-low synchronous reset - simple_alu_bind.sv: attaches checker to simple_alu without modifying RTL - simple_alu_top_fv.sv: replace bind (unsupported in open-source Yosys) with explicit wrapper that instantiates DUT and checker side-by-side - simple_alu_fv.sv: bind-based checker module observing DUT signals - simple_alu.sby: SymbiYosys config running BMC and cover tasks - README.md: verification plan tracking implemented and planned properties - .gitignore: exclude SymbiYosys output directories 2026-05-11T19:07:08+00:00 Chat 63841542+chatrajaman3@users.noreply.github.com 2026-05-11T19:07:08+00:00 urn:sha1:4569171217211a0f45297fc129e4b009de5d11a7 Closes: #1 Acked-by: Colin Yeung <colinyeung.main@gmail.com> Co-authored-by: Chathil Rajamanthree <chathil.rajaman3@gmail.com> Reviewed-by: Warrick Lo <wlo@warricklo.net> 2026-05-08T08:55:51+00:00 Warrick Lo wlo@warricklo.net 2026-05-08T08:55:51+00:00 urn:sha1:714557cb66f5be11a77d45ec51c046addf34050f Signed-off-by: Warrick Lo <wlo@warricklo.net>