montreal, branch feature/core

Minor refactor to regfile formal test module

2026-06-20T11:50:19+00:00

Signed-off-by: Warrick Lo

Add formal verification for regfile

2026-06-19T06:20:11+00:00

Successfully verifies the following requirements: * REQ-REGFILE-010 * REQ-REGFILE-020 * REQ-REGFILE-030 * REQ-REGFILE-041 * REQ-REGFILE-042 * REQ-REGFILE-043 * REQ-REGFILE-050 * REQ-REGFILE-051 * REQ-REGFILE-052 * REQ-REGFILE-053 * REQ-REGFILE-060 Verified through construction of regfile: * REQ-REGFILE-040 See-also: #14 Signed-off-by: Warrick Lo

Move typedefs to types.svh from montreal_pkg

2026-06-18T16:39:41+00:00

Yosys has poor support of packaged types. We will move typedefs to header files to prepare for formal verification with sby and the Tiny Tapeout flow later on, which uses yosys. Additionally, a debug port has been exposed to help verify the internal state of the regfile registers. Signed-off-by: Warrick Lo

Sync with 'master'

2026-06-17T00:52:01+00:00

Signed-off-by: Warrick Lo

Move design parameters to config_pkg

2026-06-17T00:44:02+00:00

Signed-off-by: Warrick Lo

regfile: refactor: 'chunks' are now 'slices'

2026-06-16T22:13:10+00:00

The term 'slice' is more consistent with old CPU architectures and academic literature. Signed-off-by: Warrick Lo

Merge branch 'crajaman/top-level-rtl'

2026-06-16T16:21:34+00:00

Closes: #12 Reviewed-by: Warrick Lo

Merge pull request #10 from ubc-asic/feature/core

2026-06-16T11:29:14+00:00

Implement register file

Add asynchronous reset to register file

2026-06-15T21:57:20+00:00

Signed-off-by: Warrick Lo

Rename top-level module to prevent clashes

2026-06-15T01:18:32+00:00

Also fixes linter errors, whitespace, and copyright. Top-level module name MUST be unique to avoid collisions with other projects in the shuttle run. The port list MUST also exactly follow the Tiny Tapeout template, so a comment has been added to emphasise this. Signed-off-by: Warrick Lo