montreal/rtl, branch feature/shifter

Implement slice-serial shifter

2026-07-05T06:48:05+00:00

Processes one slice per cycle. Supports logical left, logical right, and arithmetic right shifts. Assumes inputs are stable for the duration of the word. Also assumes slices are presented in the correct order. Signed-off-by: Warrick Lo

Clean up ALU before merge

2026-06-23T02:55:02+00:00

Co-authored-by: Warrick Lo Signed-off-by: Warrick Lo

Implement XOR, OR, AND logical operations in sliced ALU

2026-06-23T02:52:30+00:00

Signed-off-by: MyDariell

Implement ADD and SUB operations in sliced ALU

2026-06-22T01:55:45+00:00

Signed-off-by: Dariell Sugiaman

Add basic ALU skeleton

2026-06-20T20:18:38+00:00

Signed-off-by: Warrick Lo

Move typedefs to types.svh from montreal_pkg

2026-06-18T16:39:41+00:00

Yosys has poor support of packaged types. We will move typedefs to header files to prepare for formal verification with sby and the Tiny Tapeout flow later on, which uses yosys. Additionally, a debug port has been exposed to help verify the internal state of the regfile registers. Signed-off-by: Warrick Lo

Sync with 'master'

2026-06-17T00:52:01+00:00

Signed-off-by: Warrick Lo

Move design parameters to config_pkg

2026-06-17T00:44:02+00:00

Signed-off-by: Warrick Lo

regfile: refactor: 'chunks' are now 'slices'

2026-06-16T22:13:10+00:00

The term 'slice' is more consistent with old CPU architectures and academic literature. Signed-off-by: Warrick Lo

Merge branch 'crajaman/top-level-rtl'

2026-06-16T16:21:34+00:00

Closes: #12 Reviewed-by: Warrick Lo