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<title>montreal/rtl, branch master</title>
<subtitle>RV32E core for TinyTapeout, codename "Montréal". Mirror of https://github.com/ubc-asic/montreal.git.
</subtitle>
<id>https://git.warricklo.net/montreal/atom?h=master</id>
<link rel='self' href='https://git.warricklo.net/montreal/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.warricklo.net/montreal/'/>
<updated>2026-06-18T16:39:41+00:00</updated>
<entry>
<title>Move typedefs to types.svh from montreal_pkg</title>
<updated>2026-06-18T16:39:41+00:00</updated>
<author>
<name>Warrick Lo</name>
<email>wlo@warricklo.net</email>
</author>
<published>2026-06-18T16:39:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.warricklo.net/montreal/commit/?id=2455fed25341b39d505bcdad9ae2b07c6cd42a73'/>
<id>urn:sha1:2455fed25341b39d505bcdad9ae2b07c6cd42a73</id>
<content type='text'>
Yosys has poor support of packaged types. We will move typedefs to
header files to prepare for formal verification with sby and the
Tiny Tapeout flow later on, which uses yosys.

Additionally, a debug port has been exposed to help verify the internal
state of the regfile registers.

Signed-off-by: Warrick Lo &lt;wlo@warricklo.net&gt;
</content>
</entry>
<entry>
<title>Sync with 'master'</title>
<updated>2026-06-17T00:52:01+00:00</updated>
<author>
<name>Warrick Lo</name>
<email>wlo@warricklo.net</email>
</author>
<published>2026-06-17T00:52:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.warricklo.net/montreal/commit/?id=81ca21e0db518bb45d6a60beb3bfc927bb95da62'/>
<id>urn:sha1:81ca21e0db518bb45d6a60beb3bfc927bb95da62</id>
<content type='text'>
Signed-off-by: Warrick Lo &lt;wlo@warricklo.net&gt;
</content>
</entry>
<entry>
<title>Move design parameters to config_pkg</title>
<updated>2026-06-17T00:44:02+00:00</updated>
<author>
<name>Warrick Lo</name>
<email>wlo@warricklo.net</email>
</author>
<published>2026-06-17T00:44:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.warricklo.net/montreal/commit/?id=ef9254b3303a03ea4ab3c32aaf1d79df651e3b92'/>
<id>urn:sha1:ef9254b3303a03ea4ab3c32aaf1d79df651e3b92</id>
<content type='text'>
Signed-off-by: Warrick Lo &lt;wlo@warricklo.net&gt;
</content>
</entry>
<entry>
<title>regfile: refactor: 'chunks' are now 'slices'</title>
<updated>2026-06-16T22:13:10+00:00</updated>
<author>
<name>Warrick Lo</name>
<email>wlo@warricklo.net</email>
</author>
<published>2026-06-16T22:13:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.warricklo.net/montreal/commit/?id=a22f935d827879706a9b4ae481e05f22810f8b61'/>
<id>urn:sha1:a22f935d827879706a9b4ae481e05f22810f8b61</id>
<content type='text'>
The term 'slice' is more consistent with old CPU architectures and
academic literature.

Signed-off-by: Warrick Lo &lt;wlo@warricklo.net&gt;
</content>
</entry>
<entry>
<title>Merge branch 'crajaman/top-level-rtl'</title>
<updated>2026-06-16T16:21:34+00:00</updated>
<author>
<name>Warrick Lo</name>
<email>wlo@warricklo.net</email>
</author>
<published>2026-06-16T16:21:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.warricklo.net/montreal/commit/?id=48833ca8998eee2abc21f3344b4564da2d1ae5fa'/>
<id>urn:sha1:48833ca8998eee2abc21f3344b4564da2d1ae5fa</id>
<content type='text'>
Closes: #12
Reviewed-by: Warrick Lo &lt;wlo@warricklo.net&gt;
</content>
</entry>
<entry>
<title>Merge pull request #10 from ubc-asic/feature/core</title>
<updated>2026-06-16T11:29:14+00:00</updated>
<author>
<name>Chat</name>
<email>63841542+chatrajaman3@users.noreply.github.com</email>
</author>
<published>2026-06-16T11:29:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.warricklo.net/montreal/commit/?id=570e5a23989a8220153f3faa29863d73f4f764ae'/>
<id>urn:sha1:570e5a23989a8220153f3faa29863d73f4f764ae</id>
<content type='text'>
Implement register file</content>
</entry>
<entry>
<title>Add asynchronous reset to register file</title>
<updated>2026-06-15T21:57:20+00:00</updated>
<author>
<name>Warrick Lo</name>
<email>wlo@warricklo.net</email>
</author>
<published>2026-06-15T21:57:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.warricklo.net/montreal/commit/?id=33e2b4bc3a82c5e1246d1def2e14b04cc3cc45ad'/>
<id>urn:sha1:33e2b4bc3a82c5e1246d1def2e14b04cc3cc45ad</id>
<content type='text'>
Signed-off-by: Warrick Lo &lt;wlo@warricklo.net&gt;
</content>
</entry>
<entry>
<title>Rename top-level module to prevent clashes</title>
<updated>2026-06-15T01:18:32+00:00</updated>
<author>
<name>Warrick Lo</name>
<email>wlo@warricklo.net</email>
</author>
<published>2026-06-15T01:18:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.warricklo.net/montreal/commit/?id=eef204455c692cee60e3713bad6c7428627b3672'/>
<id>urn:sha1:eef204455c692cee60e3713bad6c7428627b3672</id>
<content type='text'>
Also fixes linter errors, whitespace, and copyright.

Top-level module name MUST be unique to avoid collisions with other
projects in the shuttle run.

The port list MUST also exactly follow the Tiny Tapeout template, so a
comment has been added to emphasise this.

Signed-off-by: Warrick Lo &lt;wlo@warricklo.net&gt;
</content>
</entry>
<entry>
<title>Add top-level and QSPI controller modules</title>
<updated>2026-06-14T23:21:08+00:00</updated>
<author>
<name>Chat</name>
<email>63841542+chatrajaman3@users.noreply.github.com</email>
</author>
<published>2026-06-14T23:21:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.warricklo.net/montreal/commit/?id=577ad51f728a56b1c2244cb21a563564e62999b6'/>
<id>urn:sha1:577ad51f728a56b1c2244cb21a563564e62999b6</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Pass linter</title>
<updated>2026-05-19T08:31:06+00:00</updated>
<author>
<name>Chat</name>
<email>63841542+chatrajaman3@users.noreply.github.com</email>
</author>
<published>2026-05-19T08:31:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.warricklo.net/montreal/commit/?id=429dd4fa609a5b8c71f8cd6ae6f8d74fd59f2280'/>
<id>urn:sha1:429dd4fa609a5b8c71f8cd6ae6f8d74fd59f2280</id>
<content type='text'>
  - simple_alu.sv: rename ports with suffixes (clk_i, rst_ni, a_i, b_i,
    sel_i, y_o, overflow_o); add default case to sel case statement;
    add y_next and overflow_next combinational signals; simplify
    always_ff to only register y_next and overflow_next
  - simple_alu_fv.sv: rename ports to match RTL (clk_i, rst_ni, a_i, b_i,
    sel_i, y_i, overflow_i); remove trailing spaces
  - simple_alu_top_fv.sv: rename ports; replace .* with explicit
    connections to match updated port names
  - simple_alu_bind.sv: add missing posix newline at EOF
</content>
</entry>
</feed>
