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| author | Chat <63841542+ChillZero@users.noreply.github.com> | 2026-05-14 19:58:51 -0700 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-05-14 19:58:51 -0700 |
| commit | 1fcb70209582fd05c03919b31502deb2b7af472a (patch) | |
| tree | ff887c53b5fae0c799e7eb668f26fa17553bc98a /.gitignore | |
| parent | Tidy root directory [skip ci] (diff) | |
| download | montreal-1fcb70209582fd05c03919b31502deb2b7af472a.tar.xz montreal-1fcb70209582fd05c03919b31502deb2b7af472a.zip | |
Add simple_alu RTL and formal verification
- simple_alu.sv: 32-bit ALU with add/sub, 33-bit extended overflow
detection, and active-low synchronous reset
- simple_alu_bind.sv: attaches checker to simple_alu without modifying RTL
- simple_alu_top_fv.sv: replace bind (unsupported in open-source Yosys)
with explicit wrapper that instantiates DUT and checker side-by-side
- simple_alu_fv.sv: bind-based checker module observing DUT signals
- simple_alu.sby: SymbiYosys config running BMC and cover tasks
- README.md: verification plan tracking implemented and planned properties
- .gitignore: exclude SymbiYosys output directories
Diffstat (limited to '.gitignore')
| -rw-r--r-- | .gitignore | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -4,3 +4,8 @@ *.swo .vscode .claude/ + +# SymbiYosys output +verif/formal/simple_alu/simple_alu/ +verif/formal/simple_alu/simple_alu_bmc/ +verif/formal/simple_alu/simple_alu_cover/ |