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| author | Warrick Lo <wlo@warricklo.net> | 2026-06-17 00:52:01 +0000 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-06-17 00:52:01 +0000 |
| commit | 81ca21e0db518bb45d6a60beb3bfc927bb95da62 (patch) | |
| tree | 719251f1bbdfe4c6aa436a89d58aacbaceeb6596 | |
| parent | Move design parameters to config_pkg (diff) | |
| parent | Merge branch 'crajaman/top-level-rtl' (diff) | |
| download | montreal-81ca21e0db518bb45d6a60beb3bfc927bb95da62.tar.xz montreal-81ca21e0db518bb45d6a60beb3bfc927bb95da62.zip | |
Sync with 'master'
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to '')
60 files changed, 639 insertions, 87 deletions
@@ -4,3 +4,8 @@ *.swo .vscode .claude/ + +# SymbiYosys output +verif/formal/simple_alu/simple_alu/ +verif/formal/simple_alu/simple_alu_bmc/ +verif/formal/simple_alu/simple_alu_cover/ diff --git a/README.adoc b/README.adoc new file mode 100644 index 0000000..694dcad --- /dev/null +++ b/README.adoc @@ -0,0 +1,248 @@ +Montreal +======== +:revnumber: 0.1.0-draft + +A RISC-V RV32E processor designed for TinyTapeout. + +RV32E +----- + +https://docs.riscv.org/reference/isa/unpriv/unpriv-index.html[ISA Reference] + +Reduces number of integer registers to 16 general-purpose registers +(x0-x15). Upper 16 registers consume around one quarter of the total +area of the core excluding memories, thus their removal saves around 25% +core area with a corresponding core power reduction. + +Each register is 32 bits wide. + +[cols="1,2,4", options="header"] +|=== + +| Register +| Description +| Purpose + +| x0 +| dedicated zero +| Source operand for value 0. + +| x1 +| return address +| Written by JAL/JALR. Holds address to be returned to once a function returns. +Must be saved to stack before calling another function. + +| x2 +| stack pointer +| Always points to top of the stack in RAM. Decremented to allocate space, +incremented to free it. CALLEE must restore it BEFORE returning. + +| x3 +| global pointer +| + +| x4 +| thread pointer +| + +| x5 +| alternate link reg +| Second link register for nested JAL sequences. Caller must save +if needed across a call. + +| x6 +| general scratch reg +| + +| x7 +| general scratch reg +| + +| x8 +| frame pointer +| + +| x9 +| saved register +| + +| x10 +| first function argument +| Also used to return integer results from function. + +| x11 +| second function argument +| + +| x12 +| third function argument +| + +| x13 +| fourth function argument +| + +| x14 +| fifth function argument +| + +| x15 +| sixth function argument +| + +| pc +| program counter +| Address of current instruction + +|=== + +Instruction Set +--------------- + +.Relevant opcodes for the IP. `inst[1:0] = 11`. +[cols="2*^1m,8*^2m", hrows=2] +|=== + +| +| +8+^| inst[4:2] + +| +| +| 000 +| 001 +| 010 +| 011 +| 100 +| 101 +| 110 +| 111 + +1.4+.^| inst[6:5] +| 00 +| LOAD +| +| +| MISC-MEM +| OP-IMM +| AUIPC +| +| + +| 01 +| STORE +| +| +| +| OP +| LUI +| +| + +| 10 +| +| +| +| +| +| +| +| + +| 11 +| BRANCH +| JALR +| +| JAL +| SYSTEM +| +| +| +|=== + +=== Immediate Types + +The labels `[7]`, `[20]`, and `[31]` represent the bits `inst[7]`, `inst[20]`, and `inst[31]`, respectively. + +image::docs/images/i-immediate.svg[width=100%] +image::docs/images/s-immediate.svg[width=100%] +image::docs/images/b-immediate.svg[width=100%] +image::docs/images/u-immediate.svg[width=100%] +image::docs/images/j-immediate.svg[width=100%] + +=== LUI + +image::docs/images/lui.svg[width=100%] + +=== AUIPC + +image::docs/images/auipc.svg[width=100%] + +=== OP-IMM + +image::docs/images/addi.svg[width=100%] +image::docs/images/slti.svg[width=100%] +image::docs/images/sltiu.svg[width=100%] +image::docs/images/xori.svg[width=100%] +image::docs/images/ori.svg[width=100%] +image::docs/images/andi.svg[width=100%] +image::docs/images/slli.svg[width=100%] +image::docs/images/srli.svg[width=100%] +image::docs/images/srai.svg[width=100%] + +=== OP + +image::docs/images/add.svg[width=100%] +image::docs/images/sub.svg[width=100%] +image::docs/images/slt.svg[width=100%] +image::docs/images/sltu.svg[width=100%] +image::docs/images/xor.svg[width=100%] +image::docs/images/or.svg[width=100%] +image::docs/images/and.svg[width=100%] +image::docs/images/sll.svg[width=100%] +image::docs/images/srl.svg[width=100%] +image::docs/images/sra.svg[width=100%] +image::docs/images/czero.eqz.svg[width=100%] +image::docs/images/czero.nez.svg[width=100%] + +=== JAL + +image::docs/images/jal.svg[width=100%] + +=== JALR + +image::docs/images/jalr.svg[width=100%] + +=== BRANCH + +The labels `[11]` and `[12]` represent the bits `imm[11]` and `imm[12]` respectively. + +image::docs/images/beq.svg[width=100%] +image::docs/images/bne.svg[width=100%] +image::docs/images/blt.svg[width=100%] +image::docs/images/bge.svg[width=100%] +image::docs/images/bltu.svg[width=100%] +image::docs/images/bgeu.svg[width=100%] + +=== LOAD + +image::docs/images/lb.svg[width=100%] +image::docs/images/lh.svg[width=100%] +image::docs/images/lw.svg[width=100%] +image::docs/images/lbu.svg[width=100%] +image::docs/images/lhu.svg[width=100%] + +=== STORE + +image::docs/images/sb.svg[width=100%] +image::docs/images/sh.svg[width=100%] +image::docs/images/sw.svg[width=100%] + +=== MISC-MEM + +image::docs/images/fence.svg[width=100%] + +=== SYSTEM + +image::docs/images/ecall.svg[width=100%] +image::docs/images/ebreak.svg[width=100%] diff --git a/README.md b/README.md deleted file mode 100644 index e8807da..0000000 --- a/README.md +++ /dev/null @@ -1,87 +0,0 @@ -# Montreal - -A RISC-V RV32E processor designed for TinyTapeout. - -## [RV32E](https://docs.riscv.org/reference/isa/unpriv/unpriv-index.html) - -Reduces number of integer registers to 16 general-purpose registers (x0-x15). Upper 16 registers consume around one quarter of the total area of the core excluding memories, thus their removal saves around 25% core area with a corresponding core power reduction. - -Each register is 32 bits wide. - -| Register | Description | Purpose | -| -------- | ----------- | ------- | -| x0 | dedicated zero | Source operand for value 0. | -| x1 | return address | Written by JAL/JALR. Holds address to be returned to once a function returns. Must be saved to stack before calling another function. | -| x2 | stack pointer | Always points to top of the stack in RAM. Decremented to allocate space, incremented to free it. CALLEE must restore it BEFORE returning. | -| x3 | global pointer | | -| x4 | thread pointer | | -| x5 | alternate link reg | Second link register for nested JAL sequences. Caller must save if needed across a call. | -| x6 | general scratch reg | | -| x7 | general scratch reg | | -| x8 | frame pointer | | -| x9 | saved register | | -| x10 | first function argument | Also used to return integer results from function. | -| x11 | second function argument | | -| x12 | third function argument | | -| x13 | fourth function argument | | -| x14 | fifth function argument | | -| x15 | sixth function argument | | -| pc | program counter | Address of current instruction | - -## INSTRUCTION SET -### Formats - -``` - 31 25 24 20 19 15 14 12 11 7 6 0 - +----------+--------+--------+-------+--------+----------+ -R | funct7 | rs2 | rs1 | funct3| rd | opcode | - +----------+--------+--------+-------+--------+----------+ - (src2) (src1) (dest) - +-------------------+--------+-------+--------+----------+ -I | imm[11:0] | rs1 | funct3| rd | opcode | - +-------------------+--------+-------+--------+----------+ - (src) (dest) - +----------+--------+--------+-------+--------+----------+ -I-sh | imm[11:5]|imm[4:0]| rs1 | funct3| rd | opcode | - +----------+--------+--------+-------+--------+----------+ - (src) (dest) -``` - -I-sh is the shift variant of I-type: `imm[11:5]` acts as a discriminator (like `funct7`), and `imm[4:0]` is the shift amount (shamt). - -### R-Type (Register-to-register) - -| Instruction | Description | Encoding (`funct7` \| `funct3` \| `opcode`) | -| ----------- | ----------- | ------------------------------------------ | -| ADD | Add two registers and store the result in rd. | `0000000` \| `000` \| `0110011` | -| SUB | Subtract rs2 from rs1 and store the result in rd. | `0100000` \| `000` \| `0110011` | -| SLL | Shift rs1 left by the amount in rs2 (logical), store result in rd. | `0000000` \| `001` \| `0110011` | -| SLT | Set rd to 1 if rs1 < rs2 (signed), otherwise 0. | `0000000` \| `010` \| `0110011` | -| SLTU | Set rd to 1 if rs1 < rs2 (unsigned), otherwise 0. | `0000000` \| `011` \| `0110011` | -| XOR | Bitwise XOR of rs1 and rs2, result in rd. | `0000000` \| `100` \| `0110011` | -| SRL | Shift rs1 right by the amount in rs2 (logical), store result in rd. | `0000000` \| `101` \| `0110011` | -| SRA | Shift rs1 right by the amount in rs2 (arithmetic), sign-extend result into rd. | `0100000` \| `101` \| `0110011` | -| OR | Bitwise OR of rs1 and rs2, result in rd. | `0000000` \| `110` \| `0110011` | -| AND | Bitwise AND of rs1 and rs2, result in rd. | `0000000` \| `111` \| `0110011` | - -### I-Type (Immediate) - -#### OP-IMM — Integer immediate ops (opcode `0010011`) - -| Instruction | Description | Encoding (`imm[11:0]` \| `funct3` \| `opcode`) | -| ----------- | ----------- | ----------------------------------------------- | -| ADDI | Add sign-extended 12-bit immediate to rs1, store in rd. | imm \| `000` \| `0010011` | -| SLTI | Set rd to 1 if rs1 < sign-extended imm (signed), else 0. | imm \| `010` \| `0010011` | -| SLTIU | Set rd to 1 if rs1 < sign-extended imm (unsigned), else 0. | imm \| `011` \| `0010011` | -| XORI | Bitwise XOR of rs1 and sign-extended imm, result in rd. | imm \| `100` \| `0010011` | -| ORI | Bitwise OR of rs1 and sign-extended imm, result in rd. | imm \| `110` \| `0010011` | -| ANDI | Bitwise AND of rs1 and sign-extended imm, result in rd. | imm \| `111` \| `0010011` | - -##### Shifting Instructions that carry an encoding disciminator in `imm[11:5]` -| Instruction | Description | Encoding (`imm[11:5]`\| `funct3` \| `opcode`) | -| ----------- | ----------- | ----------------------------------------------- | -| SLLI | Shift rs1 left by shamt (`imm[4:0]`), logical, store in rd. | `0000000` \| `001` \| `0010011` | -| SRLI | Shift rs1 right by shamt (`imm[4:0]`), logical, store in rd. | `0000000` \| `101` \| `0010011` | -| SRAI | Shift rs1 right by shamt (`imm[4:0]`), arithmetic, store in rd. | `0100000` \| `101` \| `0010011` | - - diff --git a/docs/images/add.svg b/docs/images/add.svg new file mode 100644 index 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\ No newline at end of file diff --git a/rtl/qspi_controller.sv b/rtl/qspi_controller.sv new file mode 100644 index 0000000..e718b50 --- /dev/null +++ b/rtl/qspi_controller.sv @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +/* + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Chathil Rajamanthree <chathil.rajaman3@gmail.com> + * + * Interface between core and QSPI Pmod + * + * https://onlinedocs.microchip.com/oxy/GUID-450989FA-38E4-4D68-AB61-15ADB29AD718-en-US-6/GUID-C2190631-B6F5-4CD7-B6DB-5267DC280E90_3.html + */ + +/* + * Pin mapping + * =========== + * + * QSPI Serial CLK + * + * QSPI CS - Active Low + * + * QSPI IO_0 + * QSPI IO_1 + * QSPI IO_2 + * QSPI IO_3 + */ +module qspi_controller ( + /* verilog_lint: waive-start port-name-suffix */ + /* Clock. */ + input wire clk, + /* Active-low reset. */ + input wire rst_n, + + /* I/O: input path. */ + input wire [7:0] uio_in, + /* I/O: output path. */ + output wire [7:0] uio_out, + /* I/O: active-high output enable. */ + output wire [7:0] uio_oe + /* verilog_lint: waive-stop port-name-suffix */ +); + + logic qspi_clk; + logic qspi_cs_n; + logic [3:0] qspi_data; + +endmodule : qspi_controller diff --git a/rtl/rv32e_core_wrapper.sv b/rtl/rv32e_core_wrapper.sv new file mode 100644 index 0000000..773b7af --- /dev/null +++ b/rtl/rv32e_core_wrapper.sv @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +/* + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Chathil Rajamanthree <chathil.rajaman3@gmail.com> + * + * Montreal RV32E Core Wrapper + * + * Provides a clean, generic bus interface for the core for easier UVM access. + */ + +module rv32e_core_wrapper (); + +endmodule : rv32e_core_wrapper diff --git a/rtl/simple_alu.sv b/rtl/simple_alu.sv new file mode 100644 index 0000000..a5ae9e7 --- /dev/null +++ b/rtl/simple_alu.sv @@ -0,0 +1,58 @@ +// Simple 32-bit ALU supporting addition and subtraction (sel=0/1). +// Outputs are registered. Overflow/underflow detected via 33-bit extended arithmetic. +// Active-low synchronous reset. Used as a sandbox for formal verification. +module simple_alu ( + + //inputs + input logic clk_i, + input logic [31:0] a_i, + input logic [31:0] b_i, + input logic sel_i, //sel = 0 -> ADD, sel = 1 -> SUB + input logic rst_ni, //active LOW sync reset + + //outputs + output logic [31:0] y_o, + output logic overflow_o +); + + logic [32:0] sum; + logic [32:0] diff; + logic [31:0] y_r; + logic overflow_r; + logic [31:0] y_next; + logic overflow_next; + + always_comb begin + sum = {1'b0, a_i} + {1'b0, b_i}; + diff = {1'b0, a_i} - {1'b0, b_i}; + + y_next = '0; + overflow_next = '0; + + if (rst_ni) begin + case (sel_i) + 0: begin + y_next = sum[31:0]; + overflow_next = sum[32]; + end + 1: begin + y_next = diff[31:0]; + overflow_next = diff[32]; + end + default: begin + y_next = '0; + overflow_next = '0; + end + endcase + end + end + + always_ff @(posedge clk_i) begin + y_r <= y_next; + overflow_r <= overflow_next; + end + + assign y_o = y_r; + assign overflow_o = overflow_r; + +endmodule diff --git a/rtl/tt_top.sv b/rtl/tt_top.sv new file mode 100644 index 0000000..5f179f6 --- /dev/null +++ b/rtl/tt_top.sv @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: Apache-2.0 OR CERN-OHL-P-2.0 */ + +/* + * Copyright 2024 Tiny Tapeout Ltd. + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Tiny Tapeout contributors + * Chathil Rajamanthree <chathil.rajaman3@gmail.com> + * + * Tiny Tapeout top-level module and QSPI PMOD controller + */ + +`default_nettype none + +/* + * Tiny Tapeout top-level wrapper. + * + * IMPORTANT: The module definition MUST follow the Tiny Tapeout specification + * exactly. Do not modify the port names. + */ +/* verilog_lint: waive module-filename */ +module tt_top_ubc_montreal ( + /* verilog_lint: waive-start port-name-suffix */ + /* Dedicated inputs. */ + input wire [7:0] ui_in, + + /* Dedicated outputs. */ + output wire [7:0] uo_out, + + /* I/O: input path. */ + input wire [7:0] uio_in, + /* I/O: output path. */ + output wire [7:0] uio_out, + /* I/O: active-high output enable. */ + output wire [7:0] uio_oe, + + /* Design enable signal. This will be 1 when the design is powered. */ + input wire ena, + /* Clock. */ + input wire clk, + /* Active-low reset. */ + input wire rst_n + /* verilog_lint: waive-stop port-name-suffix */ +); + + /* Temporary output assignments. Unused pins must be assigned to 0. */ + assign uo_out = ui_in + uio_in; + assign uio_out = '0; + assign uio_oe = '0; + + /* Connect all unused inputs to prevent warnings. */ + wire unused = &{ena, clk, rst_n, 1'b0}; + + rv32e_core_wrapper u_rv32e_core_wrapper (); + + qspi_controller u_qspi_controller ( + /* Clock. */ + .clk(), + /* Active-low reset. */ + .rst_n(), + + /* I/O: input path. */ + .uio_in(), + /* I/O: output path. */ + .uio_out(), + /* I/O: active high output enable. */ + .uio_oe() + ); + +endmodule : tt_top_ubc_montreal diff --git a/verif/formal/simple_alu/README.md b/verif/formal/simple_alu/README.md new file mode 100644 index 0000000..3355ced --- /dev/null +++ b/verif/formal/simple_alu/README.md @@ -0,0 +1,23 @@ +# simple_alu Formal Verification + +Run with: `sby -f simple_alu.sby` from this directory. + +Reference: https://yosyshq.readthedocs.io/projects/sby/en/latest/reference.html + +## Mode + +Bounded Model Check (BMC, depth=100): proves assertions hold for the first 100 clock cycles. +A counterexample waveform is generated on failure. + +Prove mode (k-induction): proves assertions hold for infinite time. Much stronger guarantee but harder to converge. Change `mode bmc` to `mode prove` in the `.sby` to use it. + +## Properties + +| Name | Status | Description | +|-------------------|-------------|------------------------------------------| +| `a_rst_check` | implemented | y == 0 one cycle after reset asserts | +| `a_rst_overflow` | planned | overflow == 0 one cycle after reset | +| `a_add` | planned | y == a+b one cycle after sel=0 | +| `a_sub` | planned | y == a-b one cycle after sel=1 | +| `a_overflow_add` | planned | overflow correct for addition | +| `a_overflow_sub` | planned | overflow correct for subtraction |
\ No newline at end of file diff --git a/verif/formal/simple_alu/simple_alu.sby b/verif/formal/simple_alu/simple_alu.sby new file mode 100644 index 0000000..cd028d9 --- /dev/null +++ b/verif/formal/simple_alu/simple_alu.sby @@ -0,0 +1,22 @@ +[tasks] +bmc +cover + +[options] +bmc: mode bmc +cover: mode cover +depth 100 + +[engines] +smtbmc + +[script] +read -formal -sv simple_alu.sv +read -formal -sv simple_alu_fv.sv +read -formal -sv simple_alu_top_fv.sv +prep -top simple_alu_top_fv + +[files] +../../../rtl/simple_alu.sv +simple_alu_fv.sv +simple_alu_top_fv.sv diff --git a/verif/formal/simple_alu/simple_alu_bind.sv b/verif/formal/simple_alu/simple_alu_bind.sv new file mode 100644 index 0000000..8ed7057 --- /dev/null +++ b/verif/formal/simple_alu/simple_alu_bind.sv @@ -0,0 +1,15 @@ +// Bind file for simple_alu formal verification. +// Attaches simple_alu_fv to every instance of simple_alu in the design. +// RTL is completely unaware of this file. +// +// bind <dut_module> <fv_module> <instance_name> (<port_connections>); + +bind simple_alu simple_alu_fv u_simple_alu_fv ( + .clk (clk), + .rst (rst), + .a (a), + .b (b), + .sel (sel), + .y (y), + .overflow (overflow) +); diff --git a/verif/formal/simple_alu/simple_alu_fv.sv b/verif/formal/simple_alu/simple_alu_fv.sv new file mode 100644 index 0000000..98c05a7 --- /dev/null +++ b/verif/formal/simple_alu/simple_alu_fv.sv @@ -0,0 +1,50 @@ +// Formal verification module for simple_alu. +// All ports are inputs - this module only observes DUT signals, never drives them. +// Instantiated via simple_alu_top_fv.sv wrapper (bind unsupported in open-source Yosys). +module simple_alu_fv ( + input logic clk_i, + input logic [31:0] a_i, + input logic [31:0] b_i, + input logic sel_i, + input logic rst_ni, + + input logic [31:0] y_i, + input logic overflow_i + ); + + // ------------------------------------------------------------------------- + // Initial assumptions - constrain starting state so solver doesn't + // explore garbage initial register values + // ------------------------------------------------------------------------- + initial assume (~rst_ni); + initial assume (y_i == '0); + initial assume (overflow_i == 1'b0); + + //assertion check: if rst deasserted, y tied to 0 + //assertions are what we want to prove, formal verification is the engine that proves it + // property p_rst_y; + // @(posedge clk_i) + // ~rst_ni |=> (y_i=='0); + // endproperty + // a_rst_y: assert property (p_rst_y) + // else $error("RESET CHECK FAILED: rst_ni=%0b y_i=%0h, expected y=0", rst_ni, y_i); + + // Reset check - y must be 0 one cycle after reset asserts (active low) + always @(posedge clk_i) begin + if ($past(~rst_ni)) begin + assert (y_i == '0); + assert (overflow_i == 0); + end + end + + // ------------------------------------------------------------------------- + // Cover statements - solver finds shortest path to reach each state + // These generate VCD traces you can inspect in GTKWave + // ------------------------------------------------------------------------- + + always @(posedge clk_i) begin + cover ($past(sel_i == 0) && overflow_i == 1'b1); // addition overflow + cover ($past(sel_i == 1) && overflow_i == 1'b1); // subtraction underflow + end + +endmodule diff --git a/verif/formal/simple_alu/simple_alu_top_fv.sv b/verif/formal/simple_alu/simple_alu_top_fv.sv new file mode 100644 index 0000000..8f1241c --- /dev/null +++ b/verif/formal/simple_alu/simple_alu_top_fv.sv @@ -0,0 +1,37 @@ +// Wrapper top module for formal verification of simple_alu. +// Instantiates the DUT and the checker side-by-side so the formal tool +// sees both. Used because open-source Yosys does not support bind. +// Note: only DUT ports are accessible here - internal signals (sum, diff) +// cannot be tapped without bind or Verific. +module simple_alu_top_fv ( + input logic clk_i, + input logic [31:0] a_i, + input logic [31:0] b_i, + input logic sel_i, + input logic rst_ni +); + logic [31:0] y; + logic overflow; + + // DUT instance + simple_alu dut ( + .clk_i (clk_i), + .a_i (a_i), + .b_i (b_i), + .sel_i (sel_i), + .rst_ni (rst_ni), + .y_o (y), + .overflow_o (overflow) + ); + + // Checker instance - observes DUT outputs + simple_alu_fv u_checker ( + .clk_i (clk_i), + .a_i (a_i), + .b_i (b_i), + .sel_i (sel_i), + .rst_ni (rst_ni), + .y_i (y), + .overflow_i (overflow) + ); +endmodule diff --git a/verif/uvm/env.sv b/verif/uvm/env.sv new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/verif/uvm/env.sv |
