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authorWarrick Lo <wlo@warricklo.net>2026-07-07 06:01:17 +0000
committerWarrick Lo <wlo@warricklo.net>2026-07-07 06:01:17 +0000
commit6c24f49f3239c79173fd180d065f8f03cfaeabfd (patch)
tree4ac1ebc964784b655cda35de979331196b19a3c2 /dv/formal/simple_alu/simple_alu_bind.sv
parentMerge branch 'feature/fu' from MyDariell (diff)
parentAdd DCO [skip ci] (diff)
downloadmontreal-6c24f49f3239c79173fd180d065f8f03cfaeabfd.tar.xz
montreal-6c24f49f3239c79173fd180d065f8f03cfaeabfd.zip
Sync with 'master'feature/fu
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to 'dv/formal/simple_alu/simple_alu_bind.sv')
-rw-r--r--dv/formal/simple_alu/simple_alu_bind.sv15
1 files changed, 15 insertions, 0 deletions
diff --git a/dv/formal/simple_alu/simple_alu_bind.sv b/dv/formal/simple_alu/simple_alu_bind.sv
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+// Bind file for simple_alu formal verification.
+// Attaches simple_alu_fv to every instance of simple_alu in the design.
+// RTL is completely unaware of this file.
+//
+// bind <dut_module> <fv_module> <instance_name> (<port_connections>);
+
+bind simple_alu simple_alu_fv u_simple_alu_fv (
+ .clk (clk),
+ .rst (rst),
+ .a (a),
+ .b (b),
+ .sel (sel),
+ .y (y),
+ .overflow (overflow)
+);