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authorWarrick Lo <wlo@warricklo.net>2026-06-24 07:58:06 +0000
committerWarrick Lo <wlo@warricklo.net>2026-06-24 07:58:06 +0000
commitadce21a91f4b55cad1126fa4d453b4d6eef79f7f (patch)
tree6132f55957a5e467cbb02e1eedecd4c75ff1e037 /dv
parentMerge branch 'feature/core' (diff)
downloadmontreal-adce21a91f4b55cad1126fa4d453b4d6eef79f7f.tar.xz
montreal-adce21a91f4b55cad1126fa4d453b4d6eef79f7f.zip
Add CI pipeline for formal verification
* Add formal verification tests with sby to CI * Fix reviewdog having insufficient API permissions See-also: #15 Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to '')
-rw-r--r--dv/formal/regfile/regfile.sby (renamed from verif/formal/regfile/regfile.sby)5
-rw-r--r--dv/formal/regfile/regfile_fv.sv (renamed from verif/formal/regfile/regfile_fv.sv)0
-rw-r--r--dv/formal/simple_alu/README.md (renamed from verif/formal/simple_alu/README.md)0
-rw-r--r--dv/formal/simple_alu/simple_alu.sby (renamed from verif/formal/simple_alu/simple_alu.sby)6
-rw-r--r--dv/formal/simple_alu/simple_alu_bind.sv (renamed from verif/formal/simple_alu/simple_alu_bind.sv)0
-rw-r--r--dv/formal/simple_alu/simple_alu_fv.sv (renamed from verif/formal/simple_alu/simple_alu_fv.sv)0
-rw-r--r--dv/formal/simple_alu/simple_alu_top_fv.sv (renamed from verif/formal/simple_alu/simple_alu_top_fv.sv)0
-rw-r--r--dv/tb/rv32e_model.py (renamed from tb/rv32e_model.py)0
-rw-r--r--dv/tb/test.sv (renamed from tb/test.sv)0
-rw-r--r--dv/uvm/env.sv (renamed from verif/uvm/env.sv)0
10 files changed, 7 insertions, 4 deletions
diff --git a/verif/formal/regfile/regfile.sby b/dv/formal/regfile/regfile.sby
index 69cb7b9..a976a29 100644
--- a/verif/formal/regfile/regfile.sby
+++ b/dv/formal/regfile/regfile.sby
@@ -1,9 +1,12 @@
[tasks]
cover
+bmc
prove
[options]
cover: mode cover
+bmc: mode bmc
+bmc: depth 50
prove: mode prove
prove: depth 20
@@ -20,4 +23,4 @@ prep -top regfile_fv
rtl/types.svh
rtl/config_pkg.sv
rtl/regfile.sv
-verif/formal/regfile/regfile_fv.sv
+dv/formal/regfile/regfile_fv.sv
diff --git a/verif/formal/regfile/regfile_fv.sv b/dv/formal/regfile/regfile_fv.sv
index 795024e..795024e 100644
--- a/verif/formal/regfile/regfile_fv.sv
+++ b/dv/formal/regfile/regfile_fv.sv
diff --git a/verif/formal/simple_alu/README.md b/dv/formal/simple_alu/README.md
index 3355ced..3355ced 100644
--- a/verif/formal/simple_alu/README.md
+++ b/dv/formal/simple_alu/README.md
diff --git a/verif/formal/simple_alu/simple_alu.sby b/dv/formal/simple_alu/simple_alu.sby
index cd028d9..4f4f3cd 100644
--- a/verif/formal/simple_alu/simple_alu.sby
+++ b/dv/formal/simple_alu/simple_alu.sby
@@ -17,6 +17,6 @@ read -formal -sv simple_alu_top_fv.sv
prep -top simple_alu_top_fv
[files]
-../../../rtl/simple_alu.sv
-simple_alu_fv.sv
-simple_alu_top_fv.sv
+rtl/simple_alu.sv
+dv/formal/simple_alu/simple_alu_fv.sv
+dv/formal/simple_alu/simple_alu_top_fv.sv
diff --git a/verif/formal/simple_alu/simple_alu_bind.sv b/dv/formal/simple_alu/simple_alu_bind.sv
index 8ed7057..8ed7057 100644
--- a/verif/formal/simple_alu/simple_alu_bind.sv
+++ b/dv/formal/simple_alu/simple_alu_bind.sv
diff --git a/verif/formal/simple_alu/simple_alu_fv.sv b/dv/formal/simple_alu/simple_alu_fv.sv
index 98c05a7..98c05a7 100644
--- a/verif/formal/simple_alu/simple_alu_fv.sv
+++ b/dv/formal/simple_alu/simple_alu_fv.sv
diff --git a/verif/formal/simple_alu/simple_alu_top_fv.sv b/dv/formal/simple_alu/simple_alu_top_fv.sv
index 8f1241c..8f1241c 100644
--- a/verif/formal/simple_alu/simple_alu_top_fv.sv
+++ b/dv/formal/simple_alu/simple_alu_top_fv.sv
diff --git a/tb/rv32e_model.py b/dv/tb/rv32e_model.py
index eda163e..eda163e 100644
--- a/tb/rv32e_model.py
+++ b/dv/tb/rv32e_model.py
diff --git a/tb/test.sv b/dv/tb/test.sv
index e69de29..e69de29 100644
--- a/tb/test.sv
+++ b/dv/tb/test.sv
diff --git a/verif/uvm/env.sv b/dv/uvm/env.sv
index e69de29..e69de29 100644
--- a/verif/uvm/env.sv
+++ b/dv/uvm/env.sv