Implement XOR, OR, AND logical operations in sliced ALU

Signed-off-by: MyDariell <Dari3llsugiaman@gmail.com>

1 files changed, 12 insertions, 3 deletions

diff --git a/rtl/alu.sv b/rtl/alu.sv
index 8805bf9..30645c1 100644
--- a/rtl/alu.sv
+++ b/rtl/alu.sv
@@ -54,11 +54,20 @@ module alu
         result_o = adder_result[SLICE_WIDTH-1:0];
       end
       /* XOR. */
-      3'b100: begin end
+      3'b100: begin 
+        result_o = a_i ^ b_i;
+        carry_d = 0; 
+      end
       /* OR. */
-      3'b110: begin end
+      3'b110: begin
+        result_o = a_i | b_i;
+        carry_d = 0;
+      end
       /* AND. */
-      3'b111: begin end
+      3'b111: begin 
+        result_o = a_i & b_i;
+        carry_d = 0;
+      end 
       default: begin end
     endcase
   end : alu_core