Merge branch 'feature/core'

* feature/core:
  Minor refactor to regfile formal test module
  Add formal verification for regfile
  Move typedefs to types.svh from montreal_pkg
  Move design parameters to config_pkg
  regfile: refactor: 'chunks' are now 'slices'

See-also: #13
See-also: #14
Reviewed-by: Warrick Lo <wlo@warricklo.net>

1 files changed, 17 insertions, 0 deletions

diff --git a/rtl/config_pkg.sv b/rtl/config_pkg.sv
new file mode 100644
index 0000000..01d6c20
--- /dev/null
+++ b/rtl/config_pkg.sv
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: CERN-OHL-P-2.0 */
+
+package config_pkg;
+
+  /* Word width as defined in the RISC-V spec. */
+  localparam int unsigned XLEN = 32;
+
+  /* We use a byte-sliced datapath, inspired by the
+   * classic bit-sliced architecture of old CPUs. */
+  localparam int unsigned SLICE_WIDTH = 8;
+
+  /* The RV32E ISA defines 16 general-purpose registers.
+   * We have two read ports to allow for pipelined reads. */
+  localparam int unsigned REG_ADDR_WIDTH     = 4;
+  localparam int unsigned REG_NUM_READ_PORTS = 2;
+
+endpackage : config_pkg