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| author | Warrick Lo <wlo@warricklo.net> | 2026-06-20 20:18:38 +0000 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-06-20 20:18:38 +0000 |
| commit | 3b76fd6f9154b7c01414f8b3f57cf0378109d1a6 (patch) | |
| tree | bb918db361f1ccfcaec9c36619cd3aea7b02ee99 /rtl/montreal_pkg.sv | |
| parent | Minor refactor to regfile formal test module (diff) | |
| download | montreal-3b76fd6f9154b7c01414f8b3f57cf0378109d1a6.tar.xz montreal-3b76fd6f9154b7c01414f8b3f57cf0378109d1a6.zip | |
Add basic ALU skeleton
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to '')
| -rw-r--r-- | rtl/montreal_pkg.sv | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/rtl/montreal_pkg.sv b/rtl/montreal_pkg.sv new file mode 100644 index 0000000..741a926 --- /dev/null +++ b/rtl/montreal_pkg.sv @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +package montreal_pkg; + + typedef logic unsigned [config_pkg::XLEN-1:0] word_t; + typedef logic unsigned [config_pkg::SLICE_WIDTH-1:0] slice_t; + + typedef enum logic [3:0] { + /* Arithmetic operations. */ + ADD = 4'b0000, + SUB = 4'b1000, + /* Logical operations. */ + XOR = 4'b0100, + OR = 4'b0110, + AND = 4'b0111, + /* Shift operations. */ + SLL = 4'b0001, + SRL = 4'b0101, + SRA = 4'b1101, + /* Conditional set operations. */ + SLT = 4'b0010, + SLTU = 4'b0011, + /* Zicond operations. */ + CZERO_EQZ = 4'b1001, + CZERO_NEZ = 4'b1011 + } fu_op_t; + +endpackage : montreal_pkg |