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| author | Chat <63841542+chatrajaman3@users.noreply.github.com> | 2026-06-14 16:21:08 -0700 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-06-14 16:21:08 -0700 |
| commit | 577ad51f728a56b1c2244cb21a563564e62999b6 (patch) | |
| tree | a00bac5e95e76d23f5fdc3a3c816ea6ce06ec51a /rtl/qspi_controller.sv | |
| parent | Update README and WaveDrom diagrams [skip ci] (diff) | |
| download | montreal-577ad51f728a56b1c2244cb21a563564e62999b6.tar.xz montreal-577ad51f728a56b1c2244cb21a563564e62999b6.zip | |
Add top-level and QSPI controller modules
Diffstat (limited to '')
| -rw-r--r-- | rtl/qspi_controller.sv | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/rtl/qspi_controller.sv b/rtl/qspi_controller.sv new file mode 100644 index 0000000..15b3c96 --- /dev/null +++ b/rtl/qspi_controller.sv @@ -0,0 +1,38 @@ +// Interface between core and QSPI pmod +// https://onlinedocs.microchip.com/oxy/GUID-450989FA-38E4-4D68-AB61-15ADB29AD718-en-US-6/GUID-C2190631-B6F5-4CD7-B6DB-5267DC280E90_3.html + +module qspi_controller ( + // Clock + input wire clk, + + // Reset (active low) + input wire rst_n, + + // Bi-directional I/O + input wire [7:0] uio_in, // IOs: Input path + output wire [7:0] uio_out, // IOs: Output path + output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) +); + + // ==================================== + // Pin mapping + // ==================================== + + // QSPI Serial CLK + + // QSPI CS - Active Low + + // QSPI IO_0 + // QSPI IO_1 + // QSPI IO_2 + // QSPI IO_3 + + + logic qspi_clk; + logic qspi_cs_n; + logic [3:0] qspi_data; + + + + +endmodule |