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| author | Warrick Lo <wlo@warricklo.net> | 2026-06-16 09:21:34 -0700 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-06-16 09:21:34 -0700 |
| commit | 48833ca8998eee2abc21f3344b4564da2d1ae5fa (patch) | |
| tree | db42ed574b65d96fcaa5cc17fe1bd51d91c8b5f4 /rtl/qspi_controller.sv | |
| parent | Merge pull request #10 from ubc-asic/feature/core (diff) | |
| parent | Rename top-level module to prevent clashes (diff) | |
| download | montreal-48833ca8998eee2abc21f3344b4564da2d1ae5fa.tar.xz montreal-48833ca8998eee2abc21f3344b4564da2d1ae5fa.zip | |
Merge branch 'crajaman/top-level-rtl'
Closes: #12
Reviewed-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to 'rtl/qspi_controller.sv')
| -rw-r--r-- | rtl/qspi_controller.sv | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/rtl/qspi_controller.sv b/rtl/qspi_controller.sv new file mode 100644 index 0000000..e718b50 --- /dev/null +++ b/rtl/qspi_controller.sv @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +/* + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Chathil Rajamanthree <chathil.rajaman3@gmail.com> + * + * Interface between core and QSPI Pmod + * + * https://onlinedocs.microchip.com/oxy/GUID-450989FA-38E4-4D68-AB61-15ADB29AD718-en-US-6/GUID-C2190631-B6F5-4CD7-B6DB-5267DC280E90_3.html + */ + +/* + * Pin mapping + * =========== + * + * QSPI Serial CLK + * + * QSPI CS - Active Low + * + * QSPI IO_0 + * QSPI IO_1 + * QSPI IO_2 + * QSPI IO_3 + */ +module qspi_controller ( + /* verilog_lint: waive-start port-name-suffix */ + /* Clock. */ + input wire clk, + /* Active-low reset. */ + input wire rst_n, + + /* I/O: input path. */ + input wire [7:0] uio_in, + /* I/O: output path. */ + output wire [7:0] uio_out, + /* I/O: active-high output enable. */ + output wire [7:0] uio_oe + /* verilog_lint: waive-stop port-name-suffix */ +); + + logic qspi_clk; + logic qspi_cs_n; + logic [3:0] qspi_data; + +endmodule : qspi_controller |