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| author | Warrick Lo <wlo@warricklo.net> | 2026-06-17 00:52:01 +0000 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-06-17 00:52:01 +0000 |
| commit | 81ca21e0db518bb45d6a60beb3bfc927bb95da62 (patch) | |
| tree | 719251f1bbdfe4c6aa436a89d58aacbaceeb6596 /rtl/rv32e_core_wrapper.sv | |
| parent | Move design parameters to config_pkg (diff) | |
| parent | Merge branch 'crajaman/top-level-rtl' (diff) | |
| download | montreal-81ca21e0db518bb45d6a60beb3bfc927bb95da62.tar.xz montreal-81ca21e0db518bb45d6a60beb3bfc927bb95da62.zip | |
Sync with 'master'
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to '')
| -rw-r--r-- | rtl/rv32e_core_wrapper.sv | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/rtl/rv32e_core_wrapper.sv b/rtl/rv32e_core_wrapper.sv new file mode 100644 index 0000000..773b7af --- /dev/null +++ b/rtl/rv32e_core_wrapper.sv @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +/* + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Chathil Rajamanthree <chathil.rajaman3@gmail.com> + * + * Montreal RV32E Core Wrapper + * + * Provides a clean, generic bus interface for the core for easier UVM access. + */ + +module rv32e_core_wrapper (); + +endmodule : rv32e_core_wrapper |