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| author | Warrick Lo <wlo@warricklo.net> | 2026-06-16 09:21:34 -0700 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-06-16 09:21:34 -0700 |
| commit | 48833ca8998eee2abc21f3344b4564da2d1ae5fa (patch) | |
| tree | db42ed574b65d96fcaa5cc17fe1bd51d91c8b5f4 /rtl/rv32e_core_wrapper.sv | |
| parent | Merge pull request #10 from ubc-asic/feature/core (diff) | |
| parent | Rename top-level module to prevent clashes (diff) | |
| download | montreal-48833ca8998eee2abc21f3344b4564da2d1ae5fa.tar.xz montreal-48833ca8998eee2abc21f3344b4564da2d1ae5fa.zip | |
Merge branch 'crajaman/top-level-rtl'
Closes: #12
Reviewed-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to 'rtl/rv32e_core_wrapper.sv')
| -rw-r--r-- | rtl/rv32e_core_wrapper.sv | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/rtl/rv32e_core_wrapper.sv b/rtl/rv32e_core_wrapper.sv new file mode 100644 index 0000000..773b7af --- /dev/null +++ b/rtl/rv32e_core_wrapper.sv @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +/* + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Chathil Rajamanthree <chathil.rajaman3@gmail.com> + * + * Montreal RV32E Core Wrapper + * + * Provides a clean, generic bus interface for the core for easier UVM access. + */ + +module rv32e_core_wrapper (); + +endmodule : rv32e_core_wrapper |