Rename top-level module to prevent clashes

Also fixes linter errors, whitespace, and copyright.

Top-level module name MUST be unique to avoid collisions with other
projects in the shuttle run.

The port list MUST also exactly follow the Tiny Tapeout template, so a
comment has been added to emphasise this.

Signed-off-by: Warrick Lo <wlo@warricklo.net>

1 files changed, 59 insertions, 46 deletions

diff --git a/rtl/tt_top.sv b/rtl/tt_top.sv
index be5f40d..5f179f6 100644
--- a/rtl/tt_top.sv
+++ b/rtl/tt_top.sv
@@ -1,58 +1,71 @@
+/* SPDX-License-Identifier: Apache-2.0 OR CERN-OHL-P-2.0 */
+
 /*
- * Copyright (c) 2026 UBC ASIC
- * SPDX-License-Identifier: Apache-2.0
+ * Copyright 2024 Tiny Tapeout Ltd.
+ * Copyright 2026 UBC ASIC contributors (Montreal project).
+ * All rights reserved.
+ *
+ * Authors: Tiny Tapeout contributors
+ *          Chathil Rajamanthree <chathil.rajaman3@gmail.com>
+ *
+ * Tiny Tapeout top-level module and QSPI PMOD controller
  */
 
-// Core wrapper + QSPI PMOD controller
-
 `default_nettype none
 
-module tt_top (
-    // Dedicated inputs
-    input  wire [7:0] ui_in,
-
-    // Dedicated outputs
-    output wire [7:0] uo_out,
-
-    // Bi-directional I/O
-    input  wire [7:0] uio_in,   // IOs: Input path
-    output wire [7:0] uio_out,  // IOs: Output path
-    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
-
-    // Enable design
-    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
-
-    // Clock
-    input  wire       clk,      // clock
-
-    // Reset
-    input  wire       rst_n     // reset_n - low to reset
+/*
+ * Tiny Tapeout top-level wrapper.
+ *
+ * IMPORTANT: The module definition MUST follow the Tiny Tapeout specification
+ *            exactly. Do not modify the port names.
+ */
+/* verilog_lint: waive module-filename */
+module tt_top_ubc_montreal (
+  /* verilog_lint: waive-start port-name-suffix */
+  /* Dedicated inputs. */
+  input wire [7:0] ui_in,
+
+  /* Dedicated outputs. */
+  output wire [7:0] uo_out,
+
+  /* I/O: input path. */
+  input  wire [7:0] uio_in,
+  /* I/O: output path. */
+  output wire [7:0] uio_out,
+  /* I/O: active-high output enable. */
+  output wire [7:0] uio_oe,
+
+  /* Design enable signal. This will be 1 when the design is powered. */
+  input wire ena,
+  /* Clock. */
+  input wire clk,
+  /* Active-low reset. */
+  input wire rst_n
+  /* verilog_lint: waive-stop port-name-suffix */
 );
 
-    // All output pins must be assigned. If not used, assign to 0.
-    assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in
-    assign uio_out = 0;
-    assign uio_oe  = 0;
-
-    // List all unused inputs to prevent warnings
-    wire _unused = &{ena, clk, rst_n, 1'b0};
-
+  /* Temporary output assignments. Unused pins must be assigned to 0. */
+  assign uo_out  = ui_in + uio_in;
+  assign uio_out = '0;
+  assign uio_oe  = '0;
 
-    u_rv32e_core_wrapper rv32e_core_wrapper(
+  /* Connect all unused inputs to prevent warnings. */
+  wire unused = &{ena, clk, rst_n, 1'b0};
 
-    );
+  rv32e_core_wrapper u_rv32e_core_wrapper ();
 
+  qspi_controller u_qspi_controller (
+    /* Clock. */
+    .clk(),
+    /* Active-low reset. */
+    .rst_n(),
 
-    u_qspi_controller qspi_controller(
-        // Clock
-        .clk(),
-        
-        // Reset
-        .rst_n(),
+    /* I/O: input path. */
+    .uio_in(),
+    /* I/O: output path. */
+    .uio_out(),
+    /* I/O: active high output enable. */
+    .uio_oe()
+  );
 
-        // Bi-directional I/O
-        .uio_in(),   // IOs: Input path
-        .uio_out(),  // IOs: Output path
-        .uio_oe(),   // IOs: Enable path (active high: 0=input, 1=output)
-    );
-endmodule
+endmodule : tt_top_ubc_montreal