Implement ADD and SUB operations in sliced ALU

Signed-off-by: Dariell Sugiaman <dari3llsugiaman@gmail.com>

1 files changed, 19 insertions, 6 deletions

diff --git a/rtl/alu.sv b/rtl/alu.sv
index f5dde19..8805bf9 100644
--- a/rtl/alu.sv
+++ b/rtl/alu.sv
@@ -24,22 +24,35 @@ module alu
   /* We used Karnaugh maps here. If the encoding for fu_op_t changes, this has to be updated. */
   assign negate_b = alu_op_i[3] || (!alu_op_i[2] && alu_op_i[1]);
 
+  /* Carry signals. */
+  logic carry, carry_d, carry_q;
+
   /* Adder width is SLICE_WIDTH + 1 to account for carry-out. */
   logic [SLICE_WIDTH:0] adder_a, adder_b, adder_result;
 
-  assign adder_a = {1'b0, a_i};
-  assign adder_b = {1'b0, (b_i ^ {SLICE_WIDTH{negate_b}})};
+  /* For the first slice, carry-in must be driven to zero for addition 
+   * and one for subtraction or comparisons. All other slices use the 
+   * carry-out from the previous slice */
 
-  /* Carry signals. */
-  logic carry, carry_d, carry_q;
+  assign carry   = (count_i == '0) ? negate_b : carry_q;
 
-  assign carry = (count_i == '0) ? negate_b : carry_q;
+  /* ADD, SUB, SLT, SLTU use the same adder to computer their results*/
+  
+  assign adder_a = {1'b0, a_i};
+  assign adder_b = {1'b0, (b_i ^ {SLICE_WIDTH{negate_b}})};
+  assign adder_result = adder_a + adder_b + (SLICE_WIDTH + 1)'(carry);
+  assign carry_o = adder_result[SLICE_WIDTH];
+  assign carry_d = carry_o;
 
   /* Combinational arithmetic/logic core. */
   always_comb begin : alu_core
+    result_o = '0;
+
     unique casez (alu_op_i[2:0])
       /* ADD, SUB, SLT, SLTU. */
-      3'b0??: begin end
+      3'b0??: begin
+        result_o = adder_result[SLICE_WIDTH-1:0];
+      end
       /* XOR. */
       3'b100: begin end
       /* OR. */