Sync with 'master'

Signed-off-by: Warrick Lo <wlo@warricklo.net>

4 files changed, 192 insertions, 0 deletions

diff --git a/rtl/qspi_controller.sv b/rtl/qspi_controller.sv
new file mode 100644
index 0000000..e718b50
--- /dev/null
+++ b/rtl/qspi_controller.sv
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: CERN-OHL-P-2.0 */
+
+/*
+ * Copyright 2026 UBC ASIC contributors (Montreal project).
+ * All rights reserved.
+ *
+ * Authors: Chathil Rajamanthree <chathil.rajaman3@gmail.com>
+ *
+ * Interface between core and QSPI Pmod
+ *
+ * https://onlinedocs.microchip.com/oxy/GUID-450989FA-38E4-4D68-AB61-15ADB29AD718-en-US-6/GUID-C2190631-B6F5-4CD7-B6DB-5267DC280E90_3.html
+ */
+
+/*
+ * Pin mapping
+ * ===========
+ *
+ * QSPI Serial CLK
+ *
+ * QSPI CS - Active Low
+ *
+ * QSPI IO_0
+ * QSPI IO_1
+ * QSPI IO_2
+ * QSPI IO_3
+ */
+module qspi_controller (
+  /* verilog_lint: waive-start port-name-suffix */
+  /* Clock. */
+  input wire clk,
+  /* Active-low reset. */
+  input wire rst_n,
+
+  /* I/O: input path. */
+  input  wire [7:0] uio_in,
+  /* I/O: output path. */
+  output wire [7:0] uio_out,
+  /* I/O: active-high output enable. */
+  output wire [7:0] uio_oe
+  /* verilog_lint: waive-stop port-name-suffix */
+);
+
+  logic       qspi_clk;
+  logic       qspi_cs_n;
+  logic [3:0] qspi_data;
+
+endmodule : qspi_controller
diff --git a/rtl/rv32e_core_wrapper.sv b/rtl/rv32e_core_wrapper.sv
new file mode 100644
index 0000000..773b7af
--- /dev/null
+++ b/rtl/rv32e_core_wrapper.sv
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: CERN-OHL-P-2.0 */
+
+/*
+ * Copyright 2026 UBC ASIC contributors (Montreal project).
+ * All rights reserved.
+ *
+ * Authors: Chathil Rajamanthree <chathil.rajaman3@gmail.com>
+ *
+ * Montreal RV32E Core Wrapper
+ *
+ * Provides a clean, generic bus interface for the core for easier UVM access.
+ */
+
+module rv32e_core_wrapper ();
+
+endmodule : rv32e_core_wrapper
diff --git a/rtl/simple_alu.sv b/rtl/simple_alu.sv
new file mode 100644
index 0000000..a5ae9e7
--- /dev/null
+++ b/rtl/simple_alu.sv
@@ -0,0 +1,58 @@
+// Simple 32-bit ALU supporting addition and subtraction (sel=0/1).
+// Outputs are registered. Overflow/underflow detected via 33-bit extended arithmetic.
+// Active-low synchronous reset. Used as a sandbox for formal verification.
+module simple_alu (
+
+    //inputs
+    input logic        clk_i,
+    input logic [31:0] a_i,
+    input logic [31:0] b_i,
+    input logic        sel_i,         //sel = 0 -> ADD, sel = 1 -> SUB
+    input logic        rst_ni,        //active LOW sync reset
+
+    //outputs
+    output logic [31:0] y_o,
+    output logic        overflow_o
+);
+
+    logic [32:0] sum;
+    logic [32:0] diff;
+    logic [31:0] y_r;
+    logic        overflow_r;
+    logic [31:0] y_next;
+    logic        overflow_next;
+
+    always_comb begin
+        sum  = {1'b0, a_i} + {1'b0, b_i};
+        diff = {1'b0, a_i} - {1'b0, b_i};
+
+        y_next        = '0;
+        overflow_next = '0;
+
+        if (rst_ni) begin
+            case (sel_i)
+                0: begin
+                    y_next        = sum[31:0];
+                    overflow_next = sum[32];
+                end
+                1: begin
+                    y_next        = diff[31:0];
+                    overflow_next = diff[32];
+                end
+                default: begin
+                    y_next        = '0;
+                    overflow_next = '0;
+                end
+            endcase
+        end
+    end
+
+    always_ff @(posedge clk_i) begin
+        y_r        <= y_next;
+        overflow_r <= overflow_next;
+    end
+
+    assign y_o        = y_r;
+    assign overflow_o = overflow_r;
+
+endmodule
diff --git a/rtl/tt_top.sv b/rtl/tt_top.sv
new file mode 100644
index 0000000..5f179f6
--- /dev/null
+++ b/rtl/tt_top.sv
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: Apache-2.0 OR CERN-OHL-P-2.0 */
+
+/*
+ * Copyright 2024 Tiny Tapeout Ltd.
+ * Copyright 2026 UBC ASIC contributors (Montreal project).
+ * All rights reserved.
+ *
+ * Authors: Tiny Tapeout contributors
+ *          Chathil Rajamanthree <chathil.rajaman3@gmail.com>
+ *
+ * Tiny Tapeout top-level module and QSPI PMOD controller
+ */
+
+`default_nettype none
+
+/*
+ * Tiny Tapeout top-level wrapper.
+ *
+ * IMPORTANT: The module definition MUST follow the Tiny Tapeout specification
+ *            exactly. Do not modify the port names.
+ */
+/* verilog_lint: waive module-filename */
+module tt_top_ubc_montreal (
+  /* verilog_lint: waive-start port-name-suffix */
+  /* Dedicated inputs. */
+  input wire [7:0] ui_in,
+
+  /* Dedicated outputs. */
+  output wire [7:0] uo_out,
+
+  /* I/O: input path. */
+  input  wire [7:0] uio_in,
+  /* I/O: output path. */
+  output wire [7:0] uio_out,
+  /* I/O: active-high output enable. */
+  output wire [7:0] uio_oe,
+
+  /* Design enable signal. This will be 1 when the design is powered. */
+  input wire ena,
+  /* Clock. */
+  input wire clk,
+  /* Active-low reset. */
+  input wire rst_n
+  /* verilog_lint: waive-stop port-name-suffix */
+);
+
+  /* Temporary output assignments. Unused pins must be assigned to 0. */
+  assign uo_out  = ui_in + uio_in;
+  assign uio_out = '0;
+  assign uio_oe  = '0;
+
+  /* Connect all unused inputs to prevent warnings. */
+  wire unused = &{ena, clk, rst_n, 1'b0};
+
+  rv32e_core_wrapper u_rv32e_core_wrapper ();
+
+  qspi_controller u_qspi_controller (
+    /* Clock. */
+    .clk(),
+    /* Active-low reset. */
+    .rst_n(),
+
+    /* I/O: input path. */
+    .uio_in(),
+    /* I/O: output path. */
+    .uio_out(),
+    /* I/O: active high output enable. */
+    .uio_oe()
+  );
+
+endmodule : tt_top_ubc_montreal