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| author | Warrick Lo <wlo@warricklo.net> | 2026-06-17 00:52:01 +0000 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-06-17 00:52:01 +0000 |
| commit | 81ca21e0db518bb45d6a60beb3bfc927bb95da62 (patch) | |
| tree | 719251f1bbdfe4c6aa436a89d58aacbaceeb6596 /verif/formal/simple_alu/simple_alu_bind.sv | |
| parent | Move design parameters to config_pkg (diff) | |
| parent | Merge branch 'crajaman/top-level-rtl' (diff) | |
| download | montreal-81ca21e0db518bb45d6a60beb3bfc927bb95da62.tar.xz montreal-81ca21e0db518bb45d6a60beb3bfc927bb95da62.zip | |
Sync with 'master'
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to '')
| -rw-r--r-- | verif/formal/simple_alu/simple_alu_bind.sv | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/verif/formal/simple_alu/simple_alu_bind.sv b/verif/formal/simple_alu/simple_alu_bind.sv new file mode 100644 index 0000000..8ed7057 --- /dev/null +++ b/verif/formal/simple_alu/simple_alu_bind.sv @@ -0,0 +1,15 @@ +// Bind file for simple_alu formal verification. +// Attaches simple_alu_fv to every instance of simple_alu in the design. +// RTL is completely unaware of this file. +// +// bind <dut_module> <fv_module> <instance_name> (<port_connections>); + +bind simple_alu simple_alu_fv u_simple_alu_fv ( + .clk (clk), + .rst (rst), + .a (a), + .b (b), + .sel (sel), + .y (y), + .overflow (overflow) +); |