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authorWarrick Lo <wlo@warricklo.net>2026-06-17 00:52:01 +0000
committerWarrick Lo <wlo@warricklo.net>2026-06-17 00:52:01 +0000
commit81ca21e0db518bb45d6a60beb3bfc927bb95da62 (patch)
tree719251f1bbdfe4c6aa436a89d58aacbaceeb6596 /verif/formal/simple_alu/simple_alu_bind.sv
parentMove design parameters to config_pkg (diff)
parentMerge branch 'crajaman/top-level-rtl' (diff)
downloadmontreal-81ca21e0db518bb45d6a60beb3bfc927bb95da62.tar.xz
montreal-81ca21e0db518bb45d6a60beb3bfc927bb95da62.zip
Sync with 'master'
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to 'verif/formal/simple_alu/simple_alu_bind.sv')
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diff --git a/verif/formal/simple_alu/simple_alu_bind.sv b/verif/formal/simple_alu/simple_alu_bind.sv
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+// Bind file for simple_alu formal verification.
+// Attaches simple_alu_fv to every instance of simple_alu in the design.
+// RTL is completely unaware of this file.
+//
+// bind <dut_module> <fv_module> <instance_name> (<port_connections>);
+
+bind simple_alu simple_alu_fv u_simple_alu_fv (
+ .clk (clk),
+ .rst (rst),
+ .a (a),
+ .b (b),
+ .sel (sel),
+ .y (y),
+ .overflow (overflow)
+);