diff options
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/alu.sv | 47 | ||||
| -rw-r--r-- | rtl/montreal_pkg.sv | 28 |
2 files changed, 18 insertions, 57 deletions
@@ -1,6 +1,8 @@ -module alu - import montreal_pkg::*; -#( +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +`include "types.svh" + +module alu #( parameter int unsigned XLEN = config_pkg::XLEN, parameter int unsigned SLICE_WIDTH = config_pkg::SLICE_WIDTH, @@ -27,48 +29,35 @@ module alu /* Carry signals. */ logic carry, carry_d, carry_q; - /* Adder width is SLICE_WIDTH + 1 to account for carry-out. */ - logic [SLICE_WIDTH:0] adder_a, adder_b, adder_result; - - /* For the first slice, carry-in must be driven to zero for addition - * and one for subtraction or comparisons. All other slices use the + /* For the first slice, carry-in must be driven to zero for addition + * and one for subtraction or comparisons. All other slices use the * carry-out from the previous slice */ + assign carry = (count_i == '0) ? negate_b : carry_q; - assign carry = (count_i == '0) ? negate_b : carry_q; + /* Adder width is SLICE_WIDTH + 1 to account for carry-out. */ + logic [SLICE_WIDTH:0] adder_a, adder_b, adder_result; - /* ADD, SUB, SLT, SLTU use the same adder to computer their results*/ - assign adder_a = {1'b0, a_i}; assign adder_b = {1'b0, (b_i ^ {SLICE_WIDTH{negate_b}})}; + + /* ADD, SUB, SLT, SLTU use the same adder to computer their results*/ assign adder_result = adder_a + adder_b + (SLICE_WIDTH + 1)'(carry); + assign carry_o = adder_result[SLICE_WIDTH]; assign carry_d = carry_o; /* Combinational arithmetic/logic core. */ always_comb begin : alu_core - result_o = '0; - unique casez (alu_op_i[2:0]) /* ADD, SUB, SLT, SLTU. */ - 3'b0??: begin - result_o = adder_result[SLICE_WIDTH-1:0]; - end + 3'b0??: result_o = adder_result[SLICE_WIDTH-1:0]; /* XOR. */ - 3'b100: begin - result_o = a_i ^ b_i; - carry_d = 0; - end + 3'b100: result_o = a_i ^ b_i; /* OR. */ - 3'b110: begin - result_o = a_i | b_i; - carry_d = 0; - end + 3'b110: result_o = a_i | b_i; /* AND. */ - 3'b111: begin - result_o = a_i & b_i; - carry_d = 0; - end - default: begin end + 3'b111: result_o = a_i & b_i; + default: result_o = '0; endcase end : alu_core diff --git a/rtl/montreal_pkg.sv b/rtl/montreal_pkg.sv deleted file mode 100644 index 741a926..0000000 --- a/rtl/montreal_pkg.sv +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ - -package montreal_pkg; - - typedef logic unsigned [config_pkg::XLEN-1:0] word_t; - typedef logic unsigned [config_pkg::SLICE_WIDTH-1:0] slice_t; - - typedef enum logic [3:0] { - /* Arithmetic operations. */ - ADD = 4'b0000, - SUB = 4'b1000, - /* Logical operations. */ - XOR = 4'b0100, - OR = 4'b0110, - AND = 4'b0111, - /* Shift operations. */ - SLL = 4'b0001, - SRL = 4'b0101, - SRA = 4'b1101, - /* Conditional set operations. */ - SLT = 4'b0010, - SLTU = 4'b0011, - /* Zicond operations. */ - CZERO_EQZ = 4'b1001, - CZERO_NEZ = 4'b1011 - } fu_op_t; - -endpackage : montreal_pkg |