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2026-06-22Clean up ALU before mergeMyDariell1-0/+4
Co-authored-by: Warrick Lo <wlo@warricklo.net> Signed-off-by: Warrick Lo <wlo@warricklo.net>
2026-05-14Add simple_alu RTL and formal verificationChat1-0/+5
- simple_alu.sv: 32-bit ALU with add/sub, 33-bit extended overflow detection, and active-low synchronous reset - simple_alu_bind.sv: attaches checker to simple_alu without modifying RTL - simple_alu_top_fv.sv: replace bind (unsupported in open-source Yosys) with explicit wrapper that instantiates DUT and checker side-by-side - simple_alu_fv.sv: bind-based checker module observing DUT signals - simple_alu.sby: SymbiYosys config running BMC and cover tasks - README.md: verification plan tracking implemented and planned properties - .gitignore: exclude SymbiYosys output directories
2026-05-11Add RISCV reference cards and update READMEChat1-0/+1
Closes: #1 Acked-by: Colin Yeung <colinyeung.main@gmail.com> Co-authored-by: Chathil Rajamanthree <chathil.rajaman3@gmail.com> Reviewed-by: Warrick Lo <wlo@warricklo.net>
2026-05-08Add project scaffoldingWarrick Lo1-0/+5
Signed-off-by: Warrick Lo <wlo@warricklo.net>