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2026-05-14Add simple_alu RTL and formal verificationChat9-0/+189
- simple_alu.sv: 32-bit ALU with add/sub, 33-bit extended overflow detection, and active-low synchronous reset - simple_alu_bind.sv: attaches checker to simple_alu without modifying RTL - simple_alu_top_fv.sv: replace bind (unsupported in open-source Yosys) with explicit wrapper that instantiates DUT and checker side-by-side - simple_alu_fv.sv: bind-based checker module observing DUT signals - simple_alu.sby: SymbiYosys config running BMC and cover tasks - README.md: verification plan tracking implemented and planned properties - .gitignore: exclude SymbiYosys output directories
2026-05-14Tidy root directory [skip ci]Warrick Lo6-206/+0
Signed-off-by: Warrick Lo <wlo@warricklo.net>
2026-05-11Remove course resourceshamzah20-60/+0
2026-05-11Add RISCV reference cards and update READMEChat4-9/+40
Closes: #1 Acked-by: Colin Yeung <colinyeung.main@gmail.com> Co-authored-by: Chathil Rajamanthree <chathil.rajaman3@gmail.com> Reviewed-by: Warrick Lo <wlo@warricklo.net>
2026-05-08Update READMEWarrick Lo1-1/+3
Signed-off-by: Warrick Lo <wlo@warricklo.net>
2026-05-08Migrate binaries to Git LFS [skip ci]Warrick Lo1-2/+4
Signed-off-by: Warrick Lo <wlo@warricklo.net>
2026-05-08Add CI linter rulesWarrick Lo2-0/+6
Signed-off-by: Warrick Lo <wlo@warricklo.net>
2026-05-08Add GitHub Actions for linting and formattingWarrick Lo3-0/+28
Signed-off-by: Warrick Lo <wlo@warricklo.net>
2026-05-08Add project scaffoldingWarrick Lo3-0/+219
Signed-off-by: Warrick Lo <wlo@warricklo.net>
2026-04-26Update resourcesChat28-1/+336
2026-04-26Initial commitChat2-0/+3
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-17 14:05:04 +0000