montreal - RV32E core for TinyTapeout, codename "Montréal". Mirror of https://github.com/ubc-asic/montreal.git.

Age	Commit message (Collapse)	Author	Files	Lines
2026-05-27	Update README and WaveDrom diagrams [skip ci]	Warrick Lo	49	-93/+295
	Signed-off-by: Warrick Lo <wlo@warricklo.net>
2026-05-23	Add WaveDrom diagrams for instructions to README	Warrick Lo	1	-22/+28
	Signed-off-by: Warrick Lo <wlo@warricklo.net>
2026-05-19	Pass linter	Chat	4	-62/+83
	- simple_alu.sv: rename ports with suffixes (clk_i, rst_ni, a_i, b_i, sel_i, y_o, overflow_o); add default case to sel case statement; add y_next and overflow_next combinational signals; simplify always_ff to only register y_next and overflow_next - simple_alu_fv.sv: rename ports to match RTL (clk_i, rst_ni, a_i, b_i, sel_i, y_i, overflow_i); remove trailing spaces - simple_alu_top_fv.sv: rename ports; replace .* with explicit connections to match updated port names - simple_alu_bind.sv: add missing posix newline at EOF
2026-05-14	Add simple_alu RTL and formal verification	Chat	9	-0/+189
	- simple_alu.sv: 32-bit ALU with add/sub, 33-bit extended overflow detection, and active-low synchronous reset - simple_alu_bind.sv: attaches checker to simple_alu without modifying RTL - simple_alu_top_fv.sv: replace bind (unsupported in open-source Yosys) with explicit wrapper that instantiates DUT and checker side-by-side - simple_alu_fv.sv: bind-based checker module observing DUT signals - simple_alu.sby: SymbiYosys config running BMC and cover tasks - README.md: verification plan tracking implemented and planned properties - .gitignore: exclude SymbiYosys output directories