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The term 'slice' is more consistent with old CPU architectures and
academic literature.
Signed-off-by: Warrick Lo <wlo@warricklo.net>
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Signed-off-by: Warrick Lo <wlo@warricklo.net>
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Also fixes linter errors, whitespace, and copyright.
Top-level module name MUST be unique to avoid collisions with other
projects in the shuttle run.
The port list MUST also exactly follow the Tiny Tapeout template, so a
comment has been added to emphasise this.
Signed-off-by: Warrick Lo <wlo@warricklo.net>
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Signed-off-by: Warrick Lo <wlo@warricklo.net>
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Signed-off-by: Warrick Lo <wlo@warricklo.net>
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- simple_alu.sv: rename ports with suffixes (clk_i, rst_ni, a_i, b_i,
sel_i, y_o, overflow_o); add default case to sel case statement;
add y_next and overflow_next combinational signals; simplify
always_ff to only register y_next and overflow_next
- simple_alu_fv.sv: rename ports to match RTL (clk_i, rst_ni, a_i, b_i,
sel_i, y_i, overflow_i); remove trailing spaces
- simple_alu_top_fv.sv: rename ports; replace .* with explicit
connections to match updated port names
- simple_alu_bind.sv: add missing posix newline at EOF
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- simple_alu.sv: 32-bit ALU with add/sub, 33-bit extended overflow
detection, and active-low synchronous reset
- simple_alu_bind.sv: attaches checker to simple_alu without modifying RTL
- simple_alu_top_fv.sv: replace bind (unsupported in open-source Yosys)
with explicit wrapper that instantiates DUT and checker side-by-side
- simple_alu_fv.sv: bind-based checker module observing DUT signals
- simple_alu.sby: SymbiYosys config running BMC and cover tasks
- README.md: verification plan tracking implemented and planned properties
- .gitignore: exclude SymbiYosys output directories
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![Update README and WaveDrom diagrams [skip ci]](/montreal/commit/docs/images/xori.svg?id=59db9335448b568ccff9964aec0626a23387597f&follow=1){kind=link}