| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2026-06-22 | Implement XOR, OR, AND logical operations in sliced ALU | MyDariell | 1 | -3/+12 |
| 2026-06-21 | Implement ADD and SUB operations in sliced ALU | MyDariell | 1 | -6/+19 |
| 2026-06-20 | Add basic ALU skeleton | Warrick Lo | 1 | -0/+61 |
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index : montreal | |
| RV32E core for TinyTapeout, codename "Montréal". Mirror of https://github.com/ubc-asic/montreal.git. |
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