montreal - RV32E core for TinyTapeout, codename "Montréal". Mirror of https://github.com/ubc-asic/montreal.git.

Age	Commit message (Expand)	Author	Files	Lines
2026-06-22	Implement XOR, OR, AND logical operations in sliced ALU	MyDariell	1	-3/+12
2026-06-21	Implement ADD and SUB operations in sliced ALU	MyDariell	1	-6/+19
2026-06-20	Add basic ALU skeleton	Warrick Lo	2	-0/+89
2026-06-18	Move typedefs to types.svh from montreal_pkg	Warrick Lo	4	-13/+27
2026-06-17	Sync with 'master'	Warrick Lo	4	-0/+192
2026-06-17	Move design parameters to config_pkg	Warrick Lo	3	-10/+37
2026-06-16	regfile: refactor: 'chunks' are now 'slices'	Warrick Lo	1	-14/+14
2026-06-16	Merge branch 'crajaman/top-level-rtl'	Warrick Lo	3	-0/+134
2026-06-16	Merge pull request #10 from ubc-asic/feature/core	Chat	1	-0/+57
2026-06-15	Add asynchronous reset to register file	Warrick Lo	1	-1/+4
2026-06-14	Rename top-level module to prevent clashes	Warrick Lo	3	-85/+115
2026-06-14	Add top-level and QSPI controller modules	Chat	3	-0/+104
2026-05-19	Pass linter	Chat	1	-25/+39
2026-05-14	Add simple_alu RTL and formal verification	Chat	2	-0/+44
2026-05-14	Add register file with chunk access	Warrick Lo	1	-0/+54