From 577ad51f728a56b1c2244cb21a563564e62999b6 Mon Sep 17 00:00:00 2001 From: Chat <63841542+chatrajaman3@users.noreply.github.com> Date: Sun, 14 Jun 2026 16:21:08 -0700 Subject: Add top-level and QSPI controller modules --- rtl/qspi_controller.sv | 38 +++++++++++++++++++++++++++++++ rtl/rv32e_core_wrapper.sv | 8 +++++++ rtl/tt_top.sv | 58 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+) create mode 100644 rtl/qspi_controller.sv create mode 100644 rtl/rv32e_core_wrapper.sv create mode 100644 rtl/tt_top.sv diff --git a/rtl/qspi_controller.sv b/rtl/qspi_controller.sv new file mode 100644 index 0000000..15b3c96 --- /dev/null +++ b/rtl/qspi_controller.sv @@ -0,0 +1,38 @@ +// Interface between core and QSPI pmod +// https://onlinedocs.microchip.com/oxy/GUID-450989FA-38E4-4D68-AB61-15ADB29AD718-en-US-6/GUID-C2190631-B6F5-4CD7-B6DB-5267DC280E90_3.html + +module qspi_controller ( + // Clock + input wire clk, + + // Reset (active low) + input wire rst_n, + + // Bi-directional I/O + input wire [7:0] uio_in, // IOs: Input path + output wire [7:0] uio_out, // IOs: Output path + output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) +); + + // ==================================== + // Pin mapping + // ==================================== + + // QSPI Serial CLK + + // QSPI CS - Active Low + + // QSPI IO_0 + // QSPI IO_1 + // QSPI IO_2 + // QSPI IO_3 + + + logic qspi_clk; + logic qspi_cs_n; + logic [3:0] qspi_data; + + + + +endmodule diff --git a/rtl/rv32e_core_wrapper.sv b/rtl/rv32e_core_wrapper.sv new file mode 100644 index 0000000..8d2b5c9 --- /dev/null +++ b/rtl/rv32e_core_wrapper.sv @@ -0,0 +1,8 @@ +// Provides a clean, generic bus interface for the core +// Easier UVM access + +module rv32e_core_wrapper (); + + + +endmodule diff --git a/rtl/tt_top.sv b/rtl/tt_top.sv new file mode 100644 index 0000000..be5f40d --- /dev/null +++ b/rtl/tt_top.sv @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2026 UBC ASIC + * SPDX-License-Identifier: Apache-2.0 + */ + +// Core wrapper + QSPI PMOD controller + +`default_nettype none + +module tt_top ( + // Dedicated inputs + input wire [7:0] ui_in, + + // Dedicated outputs + output wire [7:0] uo_out, + + // Bi-directional I/O + input wire [7:0] uio_in, // IOs: Input path + output wire [7:0] uio_out, // IOs: Output path + output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) + + // Enable design + input wire ena, // always 1 when the design is powered, so you can ignore it + + // Clock + input wire clk, // clock + + // Reset + input wire rst_n // reset_n - low to reset +); + + // All output pins must be assigned. If not used, assign to 0. + assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in + assign uio_out = 0; + assign uio_oe = 0; + + // List all unused inputs to prevent warnings + wire _unused = &{ena, clk, rst_n, 1'b0}; + + + u_rv32e_core_wrapper rv32e_core_wrapper( + + ); + + + u_qspi_controller qspi_controller( + // Clock + .clk(), + + // Reset + .rst_n(), + + // Bi-directional I/O + .uio_in(), // IOs: Input path + .uio_out(), // IOs: Output path + .uio_oe(), // IOs: Enable path (active high: 0=input, 1=output) + ); +endmodule -- cgit v1.2.3 From eef204455c692cee60e3713bad6c7428627b3672 Mon Sep 17 00:00:00 2001 From: Warrick Lo Date: Sun, 14 Jun 2026 18:18:32 -0700 Subject: Rename top-level module to prevent clashes Also fixes linter errors, whitespace, and copyright. Top-level module name MUST be unique to avoid collisions with other projects in the shuttle run. The port list MUST also exactly follow the Tiny Tapeout template, so a comment has been added to emphasise this. Signed-off-by: Warrick Lo --- rtl/qspi_controller.sv | 77 +++++++++++++++++++--------------- rtl/rv32e_core_wrapper.sv | 18 +++++--- rtl/tt_top.sv | 105 ++++++++++++++++++++++++++-------------------- 3 files changed, 115 insertions(+), 85 deletions(-) diff --git a/rtl/qspi_controller.sv b/rtl/qspi_controller.sv index 15b3c96..e718b50 100644 --- a/rtl/qspi_controller.sv +++ b/rtl/qspi_controller.sv @@ -1,38 +1,47 @@ -// Interface between core and QSPI pmod -// https://onlinedocs.microchip.com/oxy/GUID-450989FA-38E4-4D68-AB61-15ADB29AD718-en-US-6/GUID-C2190631-B6F5-4CD7-B6DB-5267DC280E90_3.html - +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +/* + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Chathil Rajamanthree + * + * Interface between core and QSPI Pmod + * + * https://onlinedocs.microchip.com/oxy/GUID-450989FA-38E4-4D68-AB61-15ADB29AD718-en-US-6/GUID-C2190631-B6F5-4CD7-B6DB-5267DC280E90_3.html + */ + +/* + * Pin mapping + * =========== + * + * QSPI Serial CLK + * + * QSPI CS - Active Low + * + * QSPI IO_0 + * QSPI IO_1 + * QSPI IO_2 + * QSPI IO_3 + */ module qspi_controller ( - // Clock - input wire clk, - - // Reset (active low) - input wire rst_n, - - // Bi-directional I/O - input wire [7:0] uio_in, // IOs: Input path - output wire [7:0] uio_out, // IOs: Output path - output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) + /* verilog_lint: waive-start port-name-suffix */ + /* Clock. */ + input wire clk, + /* Active-low reset. */ + input wire rst_n, + + /* I/O: input path. */ + input wire [7:0] uio_in, + /* I/O: output path. */ + output wire [7:0] uio_out, + /* I/O: active-high output enable. */ + output wire [7:0] uio_oe + /* verilog_lint: waive-stop port-name-suffix */ ); - // ==================================== - // Pin mapping - // ==================================== - - // QSPI Serial CLK - - // QSPI CS - Active Low - - // QSPI IO_0 - // QSPI IO_1 - // QSPI IO_2 - // QSPI IO_3 - - - logic qspi_clk; - logic qspi_cs_n; - logic [3:0] qspi_data; - - - + logic qspi_clk; + logic qspi_cs_n; + logic [3:0] qspi_data; -endmodule +endmodule : qspi_controller diff --git a/rtl/rv32e_core_wrapper.sv b/rtl/rv32e_core_wrapper.sv index 8d2b5c9..773b7af 100644 --- a/rtl/rv32e_core_wrapper.sv +++ b/rtl/rv32e_core_wrapper.sv @@ -1,8 +1,16 @@ -// Provides a clean, generic bus interface for the core -// Easier UVM access - -module rv32e_core_wrapper (); +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ +/* + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Chathil Rajamanthree + * + * Montreal RV32E Core Wrapper + * + * Provides a clean, generic bus interface for the core for easier UVM access. + */ +module rv32e_core_wrapper (); -endmodule +endmodule : rv32e_core_wrapper diff --git a/rtl/tt_top.sv b/rtl/tt_top.sv index be5f40d..5f179f6 100644 --- a/rtl/tt_top.sv +++ b/rtl/tt_top.sv @@ -1,58 +1,71 @@ +/* SPDX-License-Identifier: Apache-2.0 OR CERN-OHL-P-2.0 */ + /* - * Copyright (c) 2026 UBC ASIC - * SPDX-License-Identifier: Apache-2.0 + * Copyright 2024 Tiny Tapeout Ltd. + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Tiny Tapeout contributors + * Chathil Rajamanthree + * + * Tiny Tapeout top-level module and QSPI PMOD controller */ -// Core wrapper + QSPI PMOD controller - `default_nettype none -module tt_top ( - // Dedicated inputs - input wire [7:0] ui_in, - - // Dedicated outputs - output wire [7:0] uo_out, - - // Bi-directional I/O - input wire [7:0] uio_in, // IOs: Input path - output wire [7:0] uio_out, // IOs: Output path - output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - - // Enable design - input wire ena, // always 1 when the design is powered, so you can ignore it - - // Clock - input wire clk, // clock - - // Reset - input wire rst_n // reset_n - low to reset +/* + * Tiny Tapeout top-level wrapper. + * + * IMPORTANT: The module definition MUST follow the Tiny Tapeout specification + * exactly. Do not modify the port names. + */ +/* verilog_lint: waive module-filename */ +module tt_top_ubc_montreal ( + /* verilog_lint: waive-start port-name-suffix */ + /* Dedicated inputs. */ + input wire [7:0] ui_in, + + /* Dedicated outputs. */ + output wire [7:0] uo_out, + + /* I/O: input path. */ + input wire [7:0] uio_in, + /* I/O: output path. */ + output wire [7:0] uio_out, + /* I/O: active-high output enable. */ + output wire [7:0] uio_oe, + + /* Design enable signal. This will be 1 when the design is powered. */ + input wire ena, + /* Clock. */ + input wire clk, + /* Active-low reset. */ + input wire rst_n + /* verilog_lint: waive-stop port-name-suffix */ ); - // All output pins must be assigned. If not used, assign to 0. - assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in - assign uio_out = 0; - assign uio_oe = 0; - - // List all unused inputs to prevent warnings - wire _unused = &{ena, clk, rst_n, 1'b0}; - + /* Temporary output assignments. Unused pins must be assigned to 0. */ + assign uo_out = ui_in + uio_in; + assign uio_out = '0; + assign uio_oe = '0; - u_rv32e_core_wrapper rv32e_core_wrapper( + /* Connect all unused inputs to prevent warnings. */ + wire unused = &{ena, clk, rst_n, 1'b0}; - ); + rv32e_core_wrapper u_rv32e_core_wrapper (); + qspi_controller u_qspi_controller ( + /* Clock. */ + .clk(), + /* Active-low reset. */ + .rst_n(), - u_qspi_controller qspi_controller( - // Clock - .clk(), - - // Reset - .rst_n(), + /* I/O: input path. */ + .uio_in(), + /* I/O: output path. */ + .uio_out(), + /* I/O: active high output enable. */ + .uio_oe() + ); - // Bi-directional I/O - .uio_in(), // IOs: Input path - .uio_out(), // IOs: Output path - .uio_oe(), // IOs: Enable path (active high: 0=input, 1=output) - ); -endmodule +endmodule : tt_top_ubc_montreal -- cgit v1.2.3