From 53d81ef8b8a1ddc176b355169bcd920c0fda37da Mon Sep 17 00:00:00 2001 From: Chat <63841542+chatrajaman3@users.noreply.github.com> Date: Sun, 26 Apr 2026 14:28:07 -0700 Subject: Update resources --- README.md | 62 ++++++- .../lectures/CPEN411-SlideSet10-Parallel.pptx | 3 + .../cpen411/lectures/CPEN411-SlideSet11-CUDA.pptx | 3 + .../cpen411/lectures/CPEN411-SlideSet12-GPUs.pptx | 3 + .../lectures/CPEN411-SlideSet13-Tomasulo.pptx | 3 + .../lectures/CPEN411-SlideSet14-ReorderBuffer.pptx | 3 + .../CPEN411-SlideSet15-LoadStoreProcessing.pptx | 3 + .../CPEN411-SlideSet16-BranchPredicton.pptx | 3 + .../cpen411/lectures/CPEN411-SlideSet4-ISA.pptx | 3 + .../cpen411/lectures/CPEN411-SlideSet5-Memory.pptx | 3 + .../cpen411/lectures/CPEN411-SlideSet6-Caches.pptx | 3 + .../lectures/CPEN411-SlideSet7-Virtual_Memory.pptx | 3 + .../lectures/CPEN411-SlideSet8-Pipelining.pptx | 3 + .../lectures/CPEN411-SlideSet9-MulticycleOps.pptx | 3 + .../cpen411/lectures/CPEN411_SlideSet1-Intro.pptx | 3 + .../lectures/CPEN411_SlideSet2-Fundamentals-1.pptx | 3 + .../lectures/CPEN411_SlideSet3-Fundamentals-2.pptx | 3 + .../lectures/Slide_Set_17_Memory_Consistency.pptx | 3 + .../Slide_Set_18_Cache_Coherence_Part_1.pptx | 3 + ...Set_19_Directory_Coherence_Synchronization.pptx | 3 + .../~$CPEN411-SlideSet16-BranchPredicton.pptx | 3 + ...cture-sixth-edition-a-quantitative-approach.pdf | 3 + ...gn-and-computer-architecture-risc-v-edition.pdf | 3 + single-cycle/Hardware Arch.drawio | 204 +++++++++++++++++++++ single-cycle/mem/program.hex | 0 single-cycle/rtl/regfile.sv | 0 single-cycle/tb/rv32e_model.py | 5 + single-cycle/tb/test.sv | 0 28 files changed, 336 insertions(+), 1 deletion(-) create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet10-Parallel.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet11-CUDA.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet12-GPUs.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet13-Tomasulo.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet14-ReorderBuffer.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet15-LoadStoreProcessing.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet16-BranchPredicton.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet4-ISA.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet5-Memory.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet6-Caches.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet7-Virtual_Memory.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet8-Pipelining.pptx create mode 100644 resources/cpen411/lectures/CPEN411-SlideSet9-MulticycleOps.pptx create mode 100644 resources/cpen411/lectures/CPEN411_SlideSet1-Intro.pptx create mode 100644 resources/cpen411/lectures/CPEN411_SlideSet2-Fundamentals-1.pptx create mode 100644 resources/cpen411/lectures/CPEN411_SlideSet3-Fundamentals-2.pptx create mode 100644 resources/cpen411/lectures/Slide_Set_17_Memory_Consistency.pptx create mode 100644 resources/cpen411/lectures/Slide_Set_18_Cache_Coherence_Part_1.pptx create mode 100644 resources/cpen411/lectures/Slide_Set_19_Directory_Coherence_Synchronization.pptx create mode 100644 resources/cpen411/lectures/~$CPEN411-SlideSet16-BranchPredicton.pptx create mode 100644 resources/textbooks/computer-architecture-sixth-edition-a-quantitative-approach.pdf create mode 100644 resources/textbooks/digital-design-and-computer-architecture-risc-v-edition.pdf create mode 100644 single-cycle/Hardware Arch.drawio create mode 100644 single-cycle/mem/program.hex create mode 100644 single-cycle/rtl/regfile.sv create mode 100644 single-cycle/tb/rv32e_model.py create mode 100644 single-cycle/tb/test.sv diff --git a/README.md b/README.md index d78584d..601dbb7 100644 --- a/README.md +++ b/README.md @@ -1 +1,61 @@ -# superscalar-summer \ No newline at end of file +# superscalar-summer + +## [RV32E](https://docs.riscv.org/reference/isa/unpriv/unpriv-index.html) + +Reduces number of integer registers to 16 general-purpose registers (x0-x15). Upper 16 registers consume around one quarter of the total area of the core excluding memories, thus their removal saves around 25% core area with a corresponding core power reduction. + +Each register is 32 bits wide. + +| Register | Description | Purpose | +| -------- | ----------- | ------- | +| x0 | dedicated zero | Source operand for value 0. | +| x1 | return address | Written by JAL/JALR. Holds address to be returned to once a function returns. Must be saved to stack before calling another function. | +| x2 | stack pointer | Always points to top of the stack in RAM. Decremented to allocate space, incremented to free it. CALLEE must restore it BEFORE returning. | +| x3 | global pointer | | +| x4 | thread pointer | | +| x5 | alternate link reg | Second link register for nested JAL sequences. Caller must save if needed across a call. | +| x6 | general scratch reg | | +| x7 | general scratch reg | | +| x8 | frame pointer | | +| x9 | saved register | | +| x10 | first function argument | Also used to return integer results from function. | +| x11 | second function argument | | +| x12 | third function argument | | +| x13 | fourth function argument | | +| x14 | fifth function argument | | +| x15 | sixth function argument | | +| pc | program counter | Address of current instruction | + +## INSTRUCTION SET +### R-Type (Register-to-register) + +| Instruction | Description | Encoding (`funct7` \| `funct3` \| `opcode`) | +| ----------- | ----------- | ------------------------------------------ | +| ADD | Add two registers and store the result in rd. | `0000000` \| `000` \| `0110011` | +| SUB | Subtract rs2 from rs1 and store the result in rd. | `0100000` \| `000` \| `0110011` | +| SLL | Shift rs1 left by the amount in rs2 (logical), store result in rd. | `0000000` \| `001` \| `0110011` | +| SLT | Set rd to 1 if rs1 < rs2 (signed), otherwise 0. | `0000000` \| `010` \| `0110011` | +| SLTU | Set rd to 1 if rs1 < rs2 (unsigned), otherwise 0. | `0000000` \| `011` \| `0110011` | +| XOR | Bitwise XOR of rs1 and rs2, result in rd. | `0000000` \| `100` \| `0110011` | +| SRL | Shift rs1 right by the amount in rs2 (logical), store result in rd. | `0000000` \| `101` \| `0110011` | +| SRA | Shift rs1 right by the amount in rs2 (arithmetic), sign-extend result into rd. | `0100000` \| `101` \| `0110011` | +| OR | Bitwise OR of rs1 and rs2, result in rd. | `0000000` \| `110` \| `0110011` | +| AND | Bitwise AND of rs1 and rs2, result in rd. | `0000000` \| `111` \| `0110011` | + +### I-Type (Immediate) + +`—` in `imm[11:5]` means those bits carry data (the immediate value), not an encoding discriminator. + +#### OP-IMM — Integer immediate ops (opcode `0010011`) + +| Instruction | Description | Encoding (`imm[11:5]` \| `funct3` \| `opcode`) | +| ----------- | ----------- | ----------------------------------------------- | +| ADDI | Add sign-extended 12-bit immediate to rs1, store in rd. | — \| `000` \| `0010011` | +| SLTI | Set rd to 1 if rs1 < sign-extended imm (signed), else 0. | — \| `010` \| `0010011` | +| SLTIU | Set rd to 1 if rs1 < sign-extended imm (unsigned), else 0. | — \| `011` \| `0010011` | +| XORI | Bitwise XOR of rs1 and sign-extended imm, result in rd. | — \| `100` \| `0010011` | +| ORI | Bitwise OR of rs1 and sign-extended imm, result in rd. | — \| `110` \| `0010011` | +| ANDI | Bitwise AND of rs1 and sign-extended imm, result in rd. | — \| `111` \| `0010011` | +| SLLI | Shift rs1 left by shamt (`imm[4:0]`), logical, store in rd. | `0000000` \| `001` \| `0010011` | +| SRLI | Shift rs1 right by shamt (`imm[4:0]`), logical, store in rd. | `0000000` \| `101` \| `0010011` | +| SRAI | Shift rs1 right by shamt (`imm[4:0]`), arithmetic, store in rd. | `0100000` \| `101` \| `0010011` | diff --git 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