From ef9254b3303a03ea4ab3c32aaf1d79df651e3b92 Mon Sep 17 00:00:00 2001 From: Warrick Lo Date: Wed, 17 Jun 2026 00:44:02 +0000 Subject: Move design parameters to config_pkg Signed-off-by: Warrick Lo --- rtl/config_pkg.sv | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 rtl/config_pkg.sv (limited to 'rtl/config_pkg.sv') diff --git a/rtl/config_pkg.sv b/rtl/config_pkg.sv new file mode 100644 index 0000000..0120b14 --- /dev/null +++ b/rtl/config_pkg.sv @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +package config_pkg; + + /* Word width as defined in the RISC-V spec. */ + localparam int unsigned XLEN = 32; + + /* We use a byte-sliced datapath, inspired by the + * classic bit-sliced architecture of old CPUs. */ + localparam int unsigned SLICE_WIDTH = 8; + + /* The RV32E ISA defines 16 general-purpose registers. + * We have two read ports to allow for pipelined reads. */ + localparam int unsigned REG_ADDR_WIDTH = 4; + localparam int unsigned REG_NUM_READ_PORTS = 2; + +endpackage : config_pkg -- cgit v1.2.3