From eef204455c692cee60e3713bad6c7428627b3672 Mon Sep 17 00:00:00 2001 From: Warrick Lo Date: Sun, 14 Jun 2026 18:18:32 -0700 Subject: Rename top-level module to prevent clashes Also fixes linter errors, whitespace, and copyright. Top-level module name MUST be unique to avoid collisions with other projects in the shuttle run. The port list MUST also exactly follow the Tiny Tapeout template, so a comment has been added to emphasise this. Signed-off-by: Warrick Lo --- rtl/qspi_controller.sv | 77 ++++++++++++++++++++++++++++---------------------- 1 file changed, 43 insertions(+), 34 deletions(-) (limited to 'rtl/qspi_controller.sv') diff --git a/rtl/qspi_controller.sv b/rtl/qspi_controller.sv index 15b3c96..e718b50 100644 --- a/rtl/qspi_controller.sv +++ b/rtl/qspi_controller.sv @@ -1,38 +1,47 @@ -// Interface between core and QSPI pmod -// https://onlinedocs.microchip.com/oxy/GUID-450989FA-38E4-4D68-AB61-15ADB29AD718-en-US-6/GUID-C2190631-B6F5-4CD7-B6DB-5267DC280E90_3.html - +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +/* + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Chathil Rajamanthree + * + * Interface between core and QSPI Pmod + * + * https://onlinedocs.microchip.com/oxy/GUID-450989FA-38E4-4D68-AB61-15ADB29AD718-en-US-6/GUID-C2190631-B6F5-4CD7-B6DB-5267DC280E90_3.html + */ + +/* + * Pin mapping + * =========== + * + * QSPI Serial CLK + * + * QSPI CS - Active Low + * + * QSPI IO_0 + * QSPI IO_1 + * QSPI IO_2 + * QSPI IO_3 + */ module qspi_controller ( - // Clock - input wire clk, - - // Reset (active low) - input wire rst_n, - - // Bi-directional I/O - input wire [7:0] uio_in, // IOs: Input path - output wire [7:0] uio_out, // IOs: Output path - output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) + /* verilog_lint: waive-start port-name-suffix */ + /* Clock. */ + input wire clk, + /* Active-low reset. */ + input wire rst_n, + + /* I/O: input path. */ + input wire [7:0] uio_in, + /* I/O: output path. */ + output wire [7:0] uio_out, + /* I/O: active-high output enable. */ + output wire [7:0] uio_oe + /* verilog_lint: waive-stop port-name-suffix */ ); - // ==================================== - // Pin mapping - // ==================================== - - // QSPI Serial CLK - - // QSPI CS - Active Low - - // QSPI IO_0 - // QSPI IO_1 - // QSPI IO_2 - // QSPI IO_3 - - - logic qspi_clk; - logic qspi_cs_n; - logic [3:0] qspi_data; - - - + logic qspi_clk; + logic qspi_cs_n; + logic [3:0] qspi_data; -endmodule +endmodule : qspi_controller -- cgit v1.2.3