From 1fcb70209582fd05c03919b31502deb2b7af472a Mon Sep 17 00:00:00 2001
From: Chat <63841542+ChillZero@users.noreply.github.com>
Date: Thu, 14 May 2026 19:58:51 -0700
Subject: Add simple_alu RTL and formal verification

  - simple_alu.sv: 32-bit ALU with add/sub, 33-bit extended overflow
    detection, and active-low synchronous reset
  - simple_alu_bind.sv: attaches checker to simple_alu without modifying RTL
  - simple_alu_top_fv.sv: replace bind (unsupported in open-source Yosys)
    with explicit wrapper that instantiates DUT and checker side-by-side
  - simple_alu_fv.sv: bind-based checker module observing DUT signals
  - simple_alu.sby: SymbiYosys config running BMC and cover tasks
  - README.md: verification plan tracking implemented and planned properties
  - .gitignore: exclude SymbiYosys output directories
---
 rtl/regfile.sv | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 rtl/regfile.sv

(limited to 'rtl/regfile.sv')

diff --git a/rtl/regfile.sv b/rtl/regfile.sv
new file mode 100644
index 0000000..e69de29
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