From a22f935d827879706a9b4ae481e05f22810f8b61 Mon Sep 17 00:00:00 2001 From: Warrick Lo Date: Tue, 16 Jun 2026 22:13:10 +0000 Subject: regfile: refactor: 'chunks' are now 'slices' The term 'slice' is more consistent with old CPU architectures and academic literature. Signed-off-by: Warrick Lo --- rtl/regfile.sv | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'rtl/regfile.sv') diff --git a/rtl/regfile.sv b/rtl/regfile.sv index 1758c1a..8ca992c 100644 --- a/rtl/regfile.sv +++ b/rtl/regfile.sv @@ -8,40 +8,40 @@ * Register file * * This module contains the register file for the RISC-V core. Each word is - * partitioned into chunks (default 8 bits). A global chunk selector determines - * which chunk of each word is accessed for both read and write operations. + * partitioned into slices (default 8 bits). A global slice selector determines + * which slice of each word is accessed for both read and write operations. * * The register file has one synchronous write port and a configurable number of * read ports (default 2). Register 0 is fixed to 0 for all reads. */ module regfile #( - parameter int unsigned WORD_WIDTH = 32, - parameter int unsigned ADDR_WIDTH = 4, - parameter int unsigned CHUNK_WIDTH = 8, + parameter int unsigned WORD_WIDTH = 32, + parameter int unsigned ADDR_WIDTH = 4, + parameter int unsigned SLICE_WIDTH = 8, parameter int unsigned NUM_READ_PORTS = 2, localparam int unsigned NUM_WORDS = 2 ** ADDR_WIDTH, - localparam int unsigned NUM_CHUNKS = WORD_WIDTH / CHUNK_WIDTH + localparam int unsigned NUM_SLICES = WORD_WIDTH / SLICE_WIDTH ) ( input logic clk_i, input logic rst_ni, - input logic [$clog2(NUM_CHUNKS)-1:0] chunk_sel_i, + input logic [$clog2(NUM_SLICES)-1:0] slice_sel_i, - input logic [NUM_READ_PORTS-1:0][ ADDR_WIDTH-1:0] raddr_i, - output logic [NUM_READ_PORTS-1:0][CHUNK_WIDTH-1:0] rdata_o, + input logic [NUM_READ_PORTS-1:0][ADDR_WIDTH-1:0] raddr_i, + output logic [NUM_READ_PORTS-1:0][SLICE_WIDTH-1:0] rdata_o, input logic wen_i, - input logic [ADDR_WIDTH-1:0] waddr_i, - input logic [CHUNK_WIDTH-1:0] wdata_i + input logic [ADDR_WIDTH-1:0] waddr_i, + input logic [SLICE_WIDTH-1:0] wdata_i ); logic [NUM_WORDS-1:0][WORD_WIDTH-1:0] register; always_comb begin for (int i = 0; i < NUM_READ_PORTS; i++) begin : gen_read_block - rdata_o[i] = (raddr_i[i] == 0) - ? '0 : register[raddr_i[i]][chunk_sel_i*CHUNK_WIDTH +: CHUNK_WIDTH]; + rdata_o[i] = (raddr_i[i] == '0) + ? '0 : register[raddr_i[i]][slice_sel_i*SLICE_WIDTH +: SLICE_WIDTH]; end : gen_read_block end @@ -50,7 +50,7 @@ module regfile #( register <= '0; end else if (wen_i && (waddr_i != '0)) begin /* verilog_lint: waive dff-name-style */ - register[waddr_i][chunk_sel_i*CHUNK_WIDTH +: CHUNK_WIDTH] <= wdata_i; + register[waddr_i][slice_sel_i*SLICE_WIDTH +: SLICE_WIDTH] <= wdata_i; end end -- cgit v1.2.3