From eef204455c692cee60e3713bad6c7428627b3672 Mon Sep 17 00:00:00 2001 From: Warrick Lo Date: Sun, 14 Jun 2026 18:18:32 -0700 Subject: Rename top-level module to prevent clashes Also fixes linter errors, whitespace, and copyright. Top-level module name MUST be unique to avoid collisions with other projects in the shuttle run. The port list MUST also exactly follow the Tiny Tapeout template, so a comment has been added to emphasise this. Signed-off-by: Warrick Lo --- rtl/rv32e_core_wrapper.sv | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'rtl/rv32e_core_wrapper.sv') diff --git a/rtl/rv32e_core_wrapper.sv b/rtl/rv32e_core_wrapper.sv index 8d2b5c9..773b7af 100644 --- a/rtl/rv32e_core_wrapper.sv +++ b/rtl/rv32e_core_wrapper.sv @@ -1,8 +1,16 @@ -// Provides a clean, generic bus interface for the core -// Easier UVM access - -module rv32e_core_wrapper (); +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ +/* + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Chathil Rajamanthree + * + * Montreal RV32E Core Wrapper + * + * Provides a clean, generic bus interface for the core for easier UVM access. + */ +module rv32e_core_wrapper (); -endmodule +endmodule : rv32e_core_wrapper -- cgit v1.2.3