From 4381dbcfccee329aed76158ea62a62a9b221bdd8 Mon Sep 17 00:00:00 2001 From: MyDariell Date: Mon, 22 Jun 2026 19:52:30 -0700 Subject: Implement XOR, OR, AND logical operations in sliced ALU Signed-off-by: MyDariell --- rtl/alu.sv | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'rtl') diff --git a/rtl/alu.sv b/rtl/alu.sv index 8805bf9..30645c1 100644 --- a/rtl/alu.sv +++ b/rtl/alu.sv @@ -54,11 +54,20 @@ module alu result_o = adder_result[SLICE_WIDTH-1:0]; end /* XOR. */ - 3'b100: begin end + 3'b100: begin + result_o = a_i ^ b_i; + carry_d = 0; + end /* OR. */ - 3'b110: begin end + 3'b110: begin + result_o = a_i | b_i; + carry_d = 0; + end /* AND. */ - 3'b111: begin end + 3'b111: begin + result_o = a_i & b_i; + carry_d = 0; + end default: begin end endcase end : alu_core -- cgit v1.2.3