From 30df127c74686285eadc16ed19a0f05fef508500 Mon Sep 17 00:00:00 2001 From: Warrick Lo Date: Thu, 14 May 2026 11:32:48 -0700 Subject: Add register file with chunk access Implements a RISC-V register file with byte-selectable chunk access for an 8-bit datapath architecture. Signed-off-by: Warrick Lo --- rtl/regfile.sv | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 rtl/regfile.sv (limited to 'rtl') diff --git a/rtl/regfile.sv b/rtl/regfile.sv new file mode 100644 index 0000000..39b4c79 --- /dev/null +++ b/rtl/regfile.sv @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +/* + * Copyright 2026 UBC ASIC contributors (Montreal project). + * + * Author: Warrick Lo + * + * Register file + * + * This module contains the register file for the RISC-V core. Each word is + * partitioned into chunks (default 8 bits). A global chunk selector determines + * which chunk of each word is accessed for both read and write operations. + * + * The register file has one synchronous write port and a configurable number of + * read ports (default 2). Register 0 is fixed to 0 for all reads. + */ + +module regfile #( + parameter int unsigned WORD_WIDTH = 32, + parameter int unsigned ADDR_WIDTH = 4, + parameter int unsigned CHUNK_WIDTH = 8, + parameter int unsigned NUM_READ_PORTS = 2, + + localparam int unsigned NUM_WORDS = 2 ** ADDR_WIDTH, + localparam int unsigned NUM_CHUNKS = WORD_WIDTH / CHUNK_WIDTH +) ( + input logic clk_i, + input logic [$clog2(NUM_CHUNKS)-1:0] chunk_sel_i, + + input logic [NUM_READ_PORTS-1:0][ ADDR_WIDTH-1:0] raddr_i, + output logic [NUM_READ_PORTS-1:0][CHUNK_WIDTH-1:0] rdata_o, + + input logic wen_i, + input logic [ADDR_WIDTH-1:0] waddr_i, + input logic [CHUNK_WIDTH-1:0] wdata_i +); + + logic [NUM_WORDS-1:0][WORD_WIDTH-1:0] register; + + always_comb begin + for (int i = 0; i < NUM_READ_PORTS; i++) begin : gen_read_block + rdata_o[i] = (raddr_i[i] == 0) + ? '0 : register[raddr_i[i]][chunk_sel_i*CHUNK_WIDTH +: CHUNK_WIDTH]; + end : gen_read_block + end + + always_ff @(posedge clk_i) begin + if (wen_i && (waddr_i != '0)) begin + /* verilog_lint: waive dff-name-style */ + register[waddr_i][chunk_sel_i*CHUNK_WIDTH +: CHUNK_WIDTH] <= wdata_i; + end + end + +endmodule : regfile -- cgit v1.2.3 From 33e2b4bc3a82c5e1246d1def2e14b04cc3cc45ad Mon Sep 17 00:00:00 2001 From: Warrick Lo Date: Mon, 15 Jun 2026 14:57:20 -0700 Subject: Add asynchronous reset to register file Signed-off-by: Warrick Lo --- rtl/regfile.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'rtl') diff --git a/rtl/regfile.sv b/rtl/regfile.sv index 39b4c79..1758c1a 100644 --- a/rtl/regfile.sv +++ b/rtl/regfile.sv @@ -25,6 +25,7 @@ module regfile #( localparam int unsigned NUM_CHUNKS = WORD_WIDTH / CHUNK_WIDTH ) ( input logic clk_i, + input logic rst_ni, input logic [$clog2(NUM_CHUNKS)-1:0] chunk_sel_i, input logic [NUM_READ_PORTS-1:0][ ADDR_WIDTH-1:0] raddr_i, @@ -45,7 +46,9 @@ module regfile #( end always_ff @(posedge clk_i) begin - if (wen_i && (waddr_i != '0)) begin + if (!rst_ni) begin + register <= '0; + end else if (wen_i && (waddr_i != '0)) begin /* verilog_lint: waive dff-name-style */ register[waddr_i][chunk_sel_i*CHUNK_WIDTH +: CHUNK_WIDTH] <= wdata_i; end -- cgit v1.2.3