diff options
| author | Warrick Lo <wlo@warricklo.net> | 2026-03-08 16:28:58 -0700 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-03-08 16:28:58 -0700 |
| commit | c73f0093e7a43403d63548b9484cff67204cad2c (patch) | |
| tree | 502ea563d0459e0631fdb758f90238c05f8c392f /schematic/opamp_tb_cl.sch | |
| parent | Add circuit schematic and symbol (diff) | |
| download | opamp-c73f0093e7a43403d63548b9484cff67204cad2c.tar.xz opamp-c73f0093e7a43403d63548b9484cff67204cad2c.zip | |
Add testbenches
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to '')
| -rw-r--r-- | schematic/opamp_tb_cl.sch | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/schematic/opamp_tb_cl.sch b/schematic/opamp_tb_cl.sch new file mode 100644 index 0000000..d8fa9cd --- /dev/null +++ b/schematic/opamp_tb_cl.sch @@ -0,0 +1,18 @@ +v {xschem version=3.4.8RC file_version=1.3} +G {} +K {} +V {} +S {} +F {} +E {} +C {opamp.sym} 60 50 0 0 {name=x1} +C {lab_wire.sym} 60 0 0 0 {name=p1 sig_type=std_logic lab=VDD} +C {lab_wire.sym} 60 100 2 1 {name=p2 sig_type=std_logic lab=0} +C {lab_wire.sym} 0 30 0 0 {name=p3 sig_type=std_logic lab=IP} +C {lab_wire.sym} 0 70 0 0 {name=p4 sig_type=std_logic lab=OUT} +C {lab_wire.sym} 120 50 0 1 {name=p5 sig_type=std_logic lab=OUT} +C {code_shown.sym} 180 0 0 0 {name=SPICE only_toplevel=false value=".LIB /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt +.AC DEC 1k 100m 1G + +VDD VDD 0 DC 1.8 +VIP IP 0 DC 900m AC 100u"} |