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| author | Warrick Lo <wlo@warricklo.net> | 2026-04-08 14:13:04 -0700 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-04-08 14:13:04 -0700 |
| commit | 933915574ed32e7984ad6bbfad7c18109b010ed2 (patch) | |
| tree | 5b954c1e84a29b409b897e9e6e21f99718c65a04 | |
| parent | Add screenshots (diff) | |
| download | rc4-decrypt-933915574ed32e7984ad6bbfad7c18109b010ed2.tar.xz rc4-decrypt-933915574ed32e7984ad6bbfad7c18109b010ed2.zip | |
Add improvements to SUBMISSION.md
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to '')
| -rw-r--r-- | SUBMISSION.md | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/SUBMISSION.md b/SUBMISSION.md index e1d343a..97eaef7 100644 --- a/SUBMISSION.md +++ b/SUBMISSION.md @@ -1,4 +1,7 @@ # ARC4 Cracking Competition Submission -_Describe your strategy for fast ARC4 cracking._ -_Include the original crack time from lab 3 task 5, and the improved crack time of your bonus lab.If it isn't visible in the reports, include your board name (e.g. DE1 SoC, DE10 Lite, etc.)_ +- We implemented 108 ARC4 cracking cores in parallel. +- This also required around 108 times the memory usage. +- In the future, this can be improved by using two-port memory, or by not writing the plaintext until we confirm the key is valid. +- A PLL was added for frequency synthesis using the 50 MHz clock signal. We used a conservative clock of 90 MHz with the PLL. +- The cracking can also be pipelined further in the future. |