module init(clk, rst_n, en, rdy, addr, wrdata, wren);

	input logic clk, rst_n, en;
	output logic rdy, wren;
	output logic [7:0] addr, wrdata;

	always_ff @(posedge clk) begin
		if (~rst_n) begin
			rdy <= 1'b1;
			wren <= 1'b0;
			addr <= 8'b0;
			wrdata <= 8'b0;
		end else if (rdy && en) begin
			rdy <= 1'b0;
			wren <= 1'b1;
		end else if (wren && ((wrdata + 1'b1) !== 8'b0)) begin
			addr <= addr + 1;
			wrdata <= wrdata + 1;
		end else if (wren && ((wrdata + 1'b1) == 8'b0)) begin
			rdy <= 1'b1;
			wren <= 1'b0;
			addr <= 8'b0;
			wrdata <= 8'b0;
		end
	end

endmodule: init