risc-processor, branch master
Five-stage Turing-complete RISC processor for the DE1-SoC.
https://git.warricklo.net/risc-processor/atom?h=master
2026-04-15T03:32:20+00:00
Add README
2026-04-15T03:32:20+00:00
Warrick Lo
wlo@warricklo.net
2026-04-15T03:32:20+00:00
urn:sha1:2fb22ae7f454b97d885aab6463eaedfb3681a53d
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Add testbenches, memory files, and Tcl scripts
2024-12-16T04:17:44+00:00
Warrick Lo
wlo@warricklo.net
2024-12-16T04:17:44+00:00
urn:sha1:390a49275af4708e8ab46b61f7871eed5c87307e
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Add RTL files
2024-12-16T04:16:23+00:00
Warrick Lo
wlo@warricklo.net
2024-12-16T04:16:23+00:00
urn:sha1:cf2e2cb508049d39458049a5028bbc26cbc9c34e
Signed-off-by: Warrick Lo <wlo@warricklo.net>