risc-processor/rtl/regfile.sv, branch master

risc-processor/rtl/regfile.sv, branch master Five-stage Turing-complete RISC processor for the DE1-SoC. https://git.warricklo.net/risc-processor/atom?h=master 2024-12-16T04:16:23+00:00 Add RTL files 2024-12-16T04:16:23+00:00 Warrick Lo wlo@warricklo.net 2024-12-16T04:16:23+00:00 urn:sha1:cf2e2cb508049d39458049a5028bbc26cbc9c34e Signed-off-by: Warrick Lo <wlo@warricklo.net>