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| author | Krish Thakur <69884464+kryptoish@users.noreply.github.com> | 2024-12-09 14:31:24 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-09 14:31:24 -0800 |
| commit | 5dc0e3db55e0c19cba43ded38f82c8aec7776abf (patch) | |
| tree | 06e599874a6e9b323db39e38293b7c2d90f55098 | |
| parent | Final Working Version (diff) | |
Update README.md
| -rw-r--r-- | README.md | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -1,9 +1,9 @@ -# RISC-V Machine Source Code for CPU Competition +# RISC Processor Source Code for CPU Competition -This repository contains the RISC-V machine source code used in the CPEN 211 CPU competition held at the end of the semester. +This repository contains the RISC processor source code used in the CPEN 211 CPU competition held at the end of the semester. ## Performance Overview -- **Main Branch**: Achieves **maximum 5 cycles per instruction**. +- **Main Branch**: Achieves **maximum 5 cycles per instruction** and is currently non-pipelined in SV. - **Competition Results**: Ranked **3rd place** in terms of: - Efficiency to compute multiple instructions. - Maximum clock frequency achieved. |