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diff --git a/README.md b/README.md new file mode 100644 index 0000000..6b6a671 --- /dev/null +++ b/README.md @@ -0,0 +1,14 @@ +[](https://classroom.github.com/a/H84oO7Rx) +[](https://classroom.github.com/online_ide?assignment_repo_id=17389376&assignment_repo_type=AssignmentRepo) +# starter-lab-7-bonus + +Lab 7 bonus ONLY: Do NOT use this repository for Lab 7 or your TA will not get +your code during your marking session. + +See the Lab 7 Bonus handout for detailed instructions for what you need to do +for the bonus. + +IMPORTANT: Ensure your submission includes a Quartus project file and a +Modelsim Project File and that both specify all (System)Verilog files required +to synthesize your CPU or the autograder will not be able to compile your +design and you will get zero marks for the bonus. |