From 390a49275af4708e8ab46b61f7871eed5c87307e Mon Sep 17 00:00:00 2001 From: Warrick Lo Date: Sun, 15 Dec 2024 20:17:44 -0800 Subject: Add testbenches, memory files, and Tcl scripts Signed-off-by: Warrick Lo --- tb/cpu_tb.sv | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 tb/cpu_tb.sv (limited to 'tb/cpu_tb.sv') diff --git a/tb/cpu_tb.sv b/tb/cpu_tb.sv new file mode 100644 index 0000000..deb5aad --- /dev/null +++ b/tb/cpu_tb.sv @@ -0,0 +1,39 @@ +`define M_NOP 2'b00 +`define M_READ 2'b10 +`define M_WRITE 2'b01 + +module cpu_tb; + reg err, clk, reset; + + tb_top DUT(clk, reset); + + always #5 clk = ~clk; + + initial begin + #2000; + $display("Time limit reached.\n"); + $stop; + end + + initial begin + clk = 1'b0; + reset = 1'b1; + #10; + reset = 1'b0; + end +endmodule: cpu_tb + +module tb_top(input clk, input reset); + wire write, N, V, Z; + wire [1:0] mem_cmd; + wire [8:0] mem_addr; + wire [15:0] din, dout, mem_data; + + ram #(16, 8, "data_cpu_tb.txt") MEM(clk, mem_addr[7:0], write, din, dout); + cpu CPU(clk, reset, mem_data, mem_cmd, mem_addr, din, N, V, Z); + + assign mem_data = (mem_cmd == `M_READ & ~mem_addr[8]) + ? dout : {16{1'bz}}; + assign din = {16{1'bz}}; + assign write = mem_cmd == `M_WRITE & ~mem_addr[8]; +endmodule: tb_top -- cgit v1.2.3