[![Review Assignment Due Date](https://classroom.github.com/assets/deadline-readme-button-22041afd0340ce965d47ae6ef1cefeee28c7c493a6346c4f15d667ab976d596c.svg)](https://classroom.github.com/a/H84oO7Rx) [![Open in Visual Studio Code](https://classroom.github.com/assets/open-in-vscode-2e0aaae1b6195c2367325f4f02e2d04e9abb55f0b24a779b69b11b9e10269abc.svg)](https://classroom.github.com/online_ide?assignment_repo_id=17389376&assignment_repo_type=AssignmentRepo) # starter-lab-7-bonus Lab 7 bonus ONLY: Do NOT use this repository for Lab 7 or your TA will not get your code during your marking session. See the Lab 7 Bonus handout for detailed instructions for what you need to do for the bonus. IMPORTANT: Ensure your submission includes a Quartus project file and a Modelsim Project File and that both specify all (System)Verilog files required to synthesize your CPU or the autograder will not be able to compile your design and you will get zero marks for the bonus.