Add task 5 code, state machine broken in edge cases

Signed-off-by: Warrick Lo <warrick.s.z.lo@gmail.com>

1 files changed, 42 insertions, 16 deletions

diff --git a/task5/datapath.sv b/task5/datapath.sv
index e5c3f2f..03f408d 100644
--- a/task5/datapath.sv
+++ b/task5/datapath.sv
@@ -1,17 +1,43 @@
-module datapath(input logic slow_clock, input logic fast_clock, input logic resetb,
-                input logic load_pcard1, input logic load_pcard2, input logic load_pcard3,
-                input logic load_dcard1, input logic load_dcard2, input logic load_dcard3,
-                output logic [3:0] pcard3_out,
-                output logic [3:0] pscore_out, output logic [3:0] dscore_out,
-                output logic [6:0] HEX5, output logic [6:0] HEX4, output logic [6:0] HEX3,
-                output logic [6:0] HEX2, output logic [6:0] HEX1, output logic [6:0] HEX0);
-						
-// The code describing your datapath will go here.  Your datapath 
-// will hierarchically instantiate six card7seg blocks, two scorehand
-// blocks, and a dealcard block.  The registers may either be instatiated
-// or included as sequential always blocks directly in this file.
-//
-// Follow the block diagram in the Lab 1 handout closely as you write this code.
-
-endmodule
+module datapath(slow_clock, fast_clock, resetb,
+	load_pcard1, load_pcard2, load_pcard3,
+	load_dcard1, load_dcard2, load_dcard3,
+	pcard3_out, pscore_out, dscore_out,
+	HEX5, HEX4, HEX3, HEX2, HEX1, HEX0);
 
+	input logic slow_clock, fast_clock, resetb,
+		load_pcard1, load_pcard2, load_pcard3,
+		load_dcard1, load_dcard2, load_dcard3;
+	output logic [3:0] pcard3_out, pscore_out, dscore_out;
+	output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
+
+	logic [3:0] new_card, pcard1, pcard2, pcard3, dcard1, dcard2, dcard3;
+
+	reg4 PCard1(new_card, load_pcard1, slow_clock, resetb, pcard1);
+	reg4 PCard2(new_card, load_pcard2, slow_clock, resetb, pcard2);
+	reg4 PCard3(new_card, load_pcard3, slow_clock, resetb, pcard3);
+	reg4 DCard1(new_card, load_dcard1, slow_clock, resetb, dcard1);
+	reg4 DCard2(new_card, load_dcard2, slow_clock, resetb, dcard2);
+	reg4 DCard3(new_card, load_dcard3, slow_clock, resetb, dcard3);
+
+	dealcard U0(fast_clock, resetb, new_card);
+
+	scorehand U1(pcard1, pcard2, pcard3, pscore_out);
+	scorehand U2(dcard1, dcard2, dcard3, dscore_out);
+
+	card7seg U3(pcard1, HEX0);
+	card7seg U4(pcard2, HEX1);
+	card7seg U5(pcard3, HEX2);
+	card7seg U6(dcard1, HEX3);
+	card7seg U7(dcard2, HEX4);
+	card7seg U8(dcard3, HEX5);
+endmodule: datapath
+
+module reg4(in, load, clock, reset, out);
+	input logic [3:0] in;
+	input logic load, clock, reset;
+	output logic [3:0] out;
+
+	always_ff @(posedge clock)
+		if (~reset) out <= 4'b0;
+		else if (load) out <= in;
+endmodule: reg4