Add task 5 code, state machine broken in edge cases

Signed-off-by: Warrick Lo <warrick.s.z.lo@gmail.com>

1 files changed, 12 insertions, 16 deletions

diff --git a/task5/dealcard.sv b/task5/dealcard.sv
index 2fe4e9b..5bae100 100644
--- a/task5/dealcard.sv
+++ b/task5/dealcard.sv
@@ -1,19 +1,15 @@
-// Lucky you! We are giving you this code for free. There is nothing
-// here you need to add or write.
+module dealcard(clock, resetb, new_card);
+	input logic clock, resetb;
+	output logic [3:0] new_card;
 
-module dealcard(input logic clock, input logic resetb, output logic [3:0] new_card);
-		  
-logic [3:0] dealer_card;
+	logic [3:0] dealer_card;
 
-always_ff @(posedge clock)
-  if (resetb == 0)
-     dealer_card <= 1;  
-  else
-     if (dealer_card == 13)
-	     dealer_card <= 1;
-	  else 
-	     dealer_card++;
+	always_ff @(posedge clock)
+		if (~resetb)
+			dealer_card <= 1;
+		else
+			if (dealer_card == 13) dealer_card <= 1;
+			else dealer_card++;
 
-assign new_card = dealer_card;
-
-endmodule
+	assign new_card = dealer_card;
+endmodule: dealcard