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| author | github-classroom[bot] <66690702+github-classroom[bot]@users.noreply.github.com> | 2025-09-10 21:59:56 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-10 21:59:56 +0000 |
| commit | a186a9a6be2cb0ece7ecf0bcc27e813f5534603d (patch) | |
| tree | a4cadf53c9e7c47290b54b0446de418a9880e17e /task5/scorehand.sv | |
Initial commit
Diffstat (limited to '')
| -rw-r--r-- | task5/scorehand.sv | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/task5/scorehand.sv b/task5/scorehand.sv new file mode 100644 index 0000000..d6bd6cc --- /dev/null +++ b/task5/scorehand.sv @@ -0,0 +1,8 @@ +module scorehand(input logic [3:0] card1, input logic [3:0] card2, input logic [3:0] card3, output logic [3:0] total); + +// The code describing scorehand will go here. Remember this is a combinational +// block. The function is described in the handout. Be sure to review Verilog +// notes on bitwidth mismatches and signed/unsigned numbers. + +endmodule + |