From 459ebf4989180f72a3e1ecc4cea1cea95b22609d Mon Sep 17 00:00:00 2001 From: Warrick Lo Date: Mon, 2 Feb 2026 19:55:23 -0800 Subject: Add task 4 code Signed-off-by: Warrick Lo --- task4/card7seg.sv | 25 +++- task4/datapath.sv | 58 ++++++--- task4/dealcard.sv | 29 ++--- task4/scorehand.sv | 29 ++++- task4/statemachine.sv | 62 ++++++++-- task4/task4.qsf | 327 ++++++++++++++++++++++++++++++++++++++++++++++++++ task4/task4.sv | 101 +++++++--------- 7 files changed, 523 insertions(+), 108 deletions(-) create mode 100644 task4/task4.qsf diff --git a/task4/card7seg.sv b/task4/card7seg.sv index 6de0793..f683c89 100644 --- a/task4/card7seg.sv +++ b/task4/card7seg.sv @@ -1,6 +1,21 @@ -module card7seg(input logic [3:0] card, output logic [6:0] seg7); - - // your code goes here - -endmodule +module card7seg(in, hex); + input logic [3:0] in; + output logic [6:0] hex; + always_comb case (in) + 1: hex <= 7'b0001000; + 2: hex <= 7'b0100100; + 3: hex <= 7'b0110000; + 4: hex <= 7'b0011001; + 5: hex <= 7'b0010010; + 6: hex <= 7'b0000010; + 7: hex <= 7'b1111000; + 8: hex <= 7'b0000000; + 9: hex <= 7'b0010000; + 10: hex <= 7'b1000000; + 11: hex <= 7'b1100001; + 12: hex <= 7'b0011000; + 13: hex <= 7'b0001001; + default: hex <= 7'b1111111; + endcase +endmodule: card7seg diff --git a/task4/datapath.sv b/task4/datapath.sv index 814ab3c..03f408d 100644 --- a/task4/datapath.sv +++ b/task4/datapath.sv @@ -1,17 +1,43 @@ -module datapath(input logic slow_clock, input logic fast_clock, input logic resetb, - input logic load_pcard1, input logic load_pcard2, input logic load_pcard3, - input logic load_dcard1, input logic load_dcard2, input logic load_dcard3, - output logic [3:0] pcard3_out, - output logic [3:0] pscore_out, output logic [3:0] dscore_out, - output logic [6:0] HEX5, output logic [6:0] HEX4, output logic [6:0] HEX3, - output logic [6:0] HEX2, output logic [6:0] HEX1, output logic [6:0] HEX0); - -// The code describing your datapath will go here. Your datapath -// will hierarchically instantiate six card7seg blocks, two scorehand -// blocks, and a dealcard block. The registers may either be instatiated -// or included as sequential always blocks directly in this file. -// -// Follow the block diagram in the Lab 1 handout closely as you write this code. - -endmodule +module datapath(slow_clock, fast_clock, resetb, + load_pcard1, load_pcard2, load_pcard3, + load_dcard1, load_dcard2, load_dcard3, + pcard3_out, pscore_out, dscore_out, + HEX5, HEX4, HEX3, HEX2, HEX1, HEX0); + input logic slow_clock, fast_clock, resetb, + load_pcard1, load_pcard2, load_pcard3, + load_dcard1, load_dcard2, load_dcard3; + output logic [3:0] pcard3_out, pscore_out, dscore_out; + output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5; + + logic [3:0] new_card, pcard1, pcard2, pcard3, dcard1, dcard2, dcard3; + + reg4 PCard1(new_card, load_pcard1, slow_clock, resetb, pcard1); + reg4 PCard2(new_card, load_pcard2, slow_clock, resetb, pcard2); + reg4 PCard3(new_card, load_pcard3, slow_clock, resetb, pcard3); + reg4 DCard1(new_card, load_dcard1, slow_clock, resetb, dcard1); + reg4 DCard2(new_card, load_dcard2, slow_clock, resetb, dcard2); + reg4 DCard3(new_card, load_dcard3, slow_clock, resetb, dcard3); + + dealcard U0(fast_clock, resetb, new_card); + + scorehand U1(pcard1, pcard2, pcard3, pscore_out); + scorehand U2(dcard1, dcard2, dcard3, dscore_out); + + card7seg U3(pcard1, HEX0); + card7seg U4(pcard2, HEX1); + card7seg U5(pcard3, HEX2); + card7seg U6(dcard1, HEX3); + card7seg U7(dcard2, HEX4); + card7seg U8(dcard3, HEX5); +endmodule: datapath + +module reg4(in, load, clock, reset, out); + input logic [3:0] in; + input logic load, clock, reset; + output logic [3:0] out; + + always_ff @(posedge clock) + if (~reset) out <= 4'b0; + else if (load) out <= in; +endmodule: reg4 diff --git a/task4/dealcard.sv b/task4/dealcard.sv index cd1e781..5bae100 100644 --- a/task4/dealcard.sv +++ b/task4/dealcard.sv @@ -1,20 +1,15 @@ -// Lucky you! We are giving you this code for free. There is nothing -// here you need to add or write. +module dealcard(clock, resetb, new_card); + input logic clock, resetb; + output logic [3:0] new_card; -module dealcard(input logic clock, input resetb, output logic [3:0] new_card); + logic [3:0] dealer_card; -logic [3:0] dealer_card; - -always_ff @(posedge clock) - if (resetb == 0) - dealer_card <= 1; - else - if (dealer_card == 13) - dealer_card <= 1; - else - dealer_card++; - -assign new_card = dealer_card; - -endmodule + always_ff @(posedge clock) + if (~resetb) + dealer_card <= 1; + else + if (dealer_card == 13) dealer_card <= 1; + else dealer_card++; + assign new_card = dealer_card; +endmodule: dealcard diff --git a/task4/scorehand.sv b/task4/scorehand.sv index d6bd6cc..a472873 100644 --- a/task4/scorehand.sv +++ b/task4/scorehand.sv @@ -1,8 +1,27 @@ -module scorehand(input logic [3:0] card1, input logic [3:0] card2, input logic [3:0] card3, output logic [3:0] total); +module scorehand(card1, card2, card3, total); + input logic [3:0] card1, card2, card3; + output logic [3:0] total; -// The code describing scorehand will go here. Remember this is a combinational -// block. The function is described in the handout. Be sure to review Verilog -// notes on bitwidth mismatches and signed/unsigned numbers. + logic [3:0] value1, value2, value3; + logic [4:0] sum; -endmodule + always_comb begin + /* 10 and face cards have a value of zero. */ + if (card1 >= 10) value1 = 0; + else value1 = card1; + if (card2 >= 10) value2 = 0; + else value2 = card2; + if (card3 >= 10) value3 = 0; + else value3 = card3; + /* Perform a modulo 10 operation on the total. */ + sum = value1 + value2 + value3; + if (sum >= 20) + total = sum - 5'd20; + else if (sum >= 10) + total = sum - 5'd10; + else + total = sum; + end + +endmodule: scorehand diff --git a/task4/statemachine.sv b/task4/statemachine.sv index 1a01db2..a1c3191 100644 --- a/task4/statemachine.sv +++ b/task4/statemachine.sv @@ -1,13 +1,55 @@ -module statemachine(input logic slow_clock, input logic resetb, - input logic [3:0] dscore, input logic [3:0] pscore, input logic [3:0] pcard3, - output logic load_pcard1, output logic load_pcard2, output logic load_pcard3, - output logic load_dcard1, output logic load_dcard2, output logic load_dcard3, - output logic player_win_light, output logic dealer_win_light); +`define STATE_DEAL_P1 3'b000 +`define STATE_DEAL_D1 3'b001 +`define STATE_DEAL_P2 3'b010 +`define STATE_DEAL_D2 3'b011 +`define STATE_DEAL_P3 3'b100 +`define STATE_DEAL_D3 3'b101 +`define STATE_END 3'b110 -// The code describing your state machine will go here. Remember that -// a state machine consists of next state logic, output logic, and the -// registers that hold the state. You will want to review your notes from -// CPEN 211 or equivalent if you have forgotten how to write a state machine. +module statemachine(slow_clock, resetb, dscore, pscore, pcard3, + load_pcard1, load_pcard2, load_pcard3, + load_dcard1, load_dcard2, load_dcard3, + player_win_light, dealer_win_light); -endmodule + input logic slow_clock, resetb; + input logic [3:0] dscore, pscore, pcard3; + output logic load_pcard1, load_pcard2, load_pcard3, + load_dcard1, load_dcard2, load_dcard3, + player_win_light, dealer_win_light; + logic [2:0] state; + + always_ff @(posedge slow_clock) casex ({resetb, state}) + 4'b0_xxx: + state <= `STATE_DEAL_P1; + {1'b1, `STATE_DEAL_P1}: + state <= `STATE_DEAL_D1; + {1'b1, `STATE_DEAL_D1}: + state <= `STATE_DEAL_P2; + {1'b1, `STATE_DEAL_P2}: + state <= `STATE_DEAL_D2; + {1'b1, `STATE_DEAL_D2}: + state <= `STATE_END; + {1'b1, `STATE_END}: + state <= `STATE_END; + default: + state <= `STATE_DEAL_P1; + endcase + + always_comb begin + {player_win_light, dealer_win_light, + load_pcard1, load_pcard2, load_pcard3, + load_dcard1, load_dcard2, load_dcard3} + = 8'b0; + + case (state) + `STATE_DEAL_P1: load_pcard1 = 1'b1; + `STATE_DEAL_P2: load_pcard2 = 1'b1; + `STATE_DEAL_P3: load_pcard3 = 1'b1; + `STATE_DEAL_D1: load_dcard1 = 1'b1; + `STATE_DEAL_D2: load_dcard2 = 1'b1; + `STATE_DEAL_D3: load_dcard3 = 1'b1; + `STATE_END: {player_win_light, dealer_win_light} = 2'b11; + endcase + end +endmodule: statemachine diff --git a/task4/task4.qsf b/task4/task4.qsf new file mode 100644 index 0000000..c06a96c --- /dev/null +++ b/task4/task4.qsf @@ -0,0 +1,327 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition +# Date created = 18:35:43 February 02, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# task4_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA5F31C6 +set_global_assignment -name TOP_LEVEL_ENTITY task4 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 24.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:35:43 FEBRUARY 02, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "24.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE task4.sv +set_global_assignment -name SYSTEMVERILOG_FILE statemachine.sv +set_global_assignment -name SYSTEMVERILOG_FILE scorehand.sv +set_global_assignment -name SYSTEMVERILOG_FILE dealcard.sv +set_global_assignment -name SYSTEMVERILOG_FILE datapath.sv +set_global_assignment -name SYSTEMVERILOG_FILE card7seg.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_AJ4 -to ADC_CS_N +set_location_assignment PIN_AK4 -to ADC_DIN +set_location_assignment PIN_AK3 -to ADC_DOUT +set_location_assignment PIN_AK2 -to ADC_SCLK +set_location_assignment PIN_K7 -to AUD_ADCDAT +set_location_assignment PIN_K8 -to AUD_ADCLRCK +set_location_assignment PIN_H7 -to AUD_BCLK +set_location_assignment PIN_J7 -to AUD_DACDAT +set_location_assignment PIN_H8 -to AUD_DACLRCK +set_location_assignment PIN_G7 -to AUD_XCK +set_location_assignment PIN_AF14 -to CLOCK_50 +set_location_assignment PIN_AA16 -to CLOCK2_50 +set_location_assignment PIN_Y26 -to CLOCK3_50 +set_location_assignment PIN_K14 -to CLOCK4_50 +set_location_assignment PIN_AK14 -to DRAM_ADDR[0] +set_location_assignment PIN_AH14 -to DRAM_ADDR[1] +set_location_assignment PIN_AG15 -to DRAM_ADDR[2] +set_location_assignment PIN_AE14 -to DRAM_ADDR[3] +set_location_assignment PIN_AB15 -to DRAM_ADDR[4] +set_location_assignment PIN_AC14 -to DRAM_ADDR[5] +set_location_assignment PIN_AD14 -to DRAM_ADDR[6] +set_location_assignment PIN_AF15 -to DRAM_ADDR[7] +set_location_assignment PIN_AH15 -to DRAM_ADDR[8] +set_location_assignment PIN_AG13 -to DRAM_ADDR[9] +set_location_assignment PIN_AG12 -to DRAM_ADDR[10] +set_location_assignment PIN_AH13 -to DRAM_ADDR[11] +set_location_assignment PIN_AJ14 -to DRAM_ADDR[12] +set_location_assignment PIN_AF13 -to DRAM_BA[0] +set_location_assignment PIN_AJ12 -to DRAM_BA[1] +set_location_assignment PIN_AF11 -to DRAM_CAS_N +set_location_assignment PIN_AK13 -to DRAM_CKE +set_location_assignment PIN_AH12 -to DRAM_CLK +set_location_assignment PIN_AG11 -to DRAM_CS_N +set_location_assignment PIN_AK6 -to DRAM_DQ[0] +set_location_assignment PIN_AJ7 -to DRAM_DQ[1] +set_location_assignment PIN_AK7 -to DRAM_DQ[2] +set_location_assignment PIN_AK8 -to DRAM_DQ[3] +set_location_assignment PIN_AK9 -to DRAM_DQ[4] +set_location_assignment PIN_AG10 -to DRAM_DQ[5] +set_location_assignment PIN_AK11 -to DRAM_DQ[6] +set_location_assignment PIN_AJ11 -to DRAM_DQ[7] +set_location_assignment PIN_AH10 -to DRAM_DQ[8] +set_location_assignment PIN_AJ10 -to DRAM_DQ[9] +set_location_assignment PIN_AJ9 -to DRAM_DQ[10] +set_location_assignment PIN_AH9 -to DRAM_DQ[11] +set_location_assignment PIN_AH8 -to DRAM_DQ[12] +set_location_assignment PIN_AH7 -to DRAM_DQ[13] +set_location_assignment PIN_AJ6 -to DRAM_DQ[14] +set_location_assignment PIN_AJ5 -to DRAM_DQ[15] +set_location_assignment PIN_AB13 -to DRAM_LDQM +set_location_assignment PIN_AE13 -to DRAM_RAS_N +set_location_assignment PIN_AK12 -to DRAM_UDQM +set_location_assignment PIN_AA13 -to DRAM_WE_N +set_location_assignment PIN_AA12 -to FAN_CTRL +set_location_assignment PIN_J12 -to FPGA_I2C_SCLK +set_location_assignment PIN_K12 -to FPGA_I2C_SDAT +set_location_assignment PIN_AC18 -to GPIO_0[0] +set_location_assignment PIN_AH18 -to GPIO_0[10] +set_location_assignment PIN_AH17 -to GPIO_0[11] +set_location_assignment PIN_AG16 -to GPIO_0[12] +set_location_assignment PIN_AE16 -to GPIO_0[13] +set_location_assignment PIN_AF16 -to GPIO_0[14] +set_location_assignment PIN_AG17 -to GPIO_0[15] +set_location_assignment PIN_AA18 -to GPIO_0[16] +set_location_assignment PIN_AA19 -to GPIO_0[17] +set_location_assignment PIN_AE17 -to GPIO_0[18] +set_location_assignment PIN_AC20 -to GPIO_0[19] +set_location_assignment PIN_Y17 -to GPIO_0[1] +set_location_assignment PIN_AH19 -to GPIO_0[20] +set_location_assignment PIN_AJ20 -to GPIO_0[21] +set_location_assignment PIN_AH20 -to GPIO_0[22] +set_location_assignment PIN_AK21 -to GPIO_0[23] +set_location_assignment PIN_AD19 -to GPIO_0[24] +set_location_assignment PIN_AD20 -to GPIO_0[25] +set_location_assignment PIN_AE18 -to GPIO_0[26] +set_location_assignment PIN_AE19 -to GPIO_0[27] +set_location_assignment PIN_AF20 -to GPIO_0[28] +set_location_assignment PIN_AF21 -to GPIO_0[29] +set_location_assignment PIN_AD17 -to GPIO_0[2] +set_location_assignment PIN_AF19 -to GPIO_0[30] +set_location_assignment PIN_AG21 -to GPIO_0[31] +set_location_assignment PIN_AF18 -to GPIO_0[32] +set_location_assignment PIN_AG20 -to GPIO_0[33] +set_location_assignment PIN_AG18 -to GPIO_0[34] +set_location_assignment PIN_AJ21 -to GPIO_0[35] +set_location_assignment PIN_Y18 -to GPIO_0[3] +set_location_assignment PIN_AK16 -to GPIO_0[4] +set_location_assignment PIN_AK18 -to GPIO_0[5] +set_location_assignment PIN_AK19 -to GPIO_0[6] +set_location_assignment PIN_AJ19 -to GPIO_0[7] +set_location_assignment PIN_AJ17 -to GPIO_0[8] +set_location_assignment PIN_AJ16 -to GPIO_0[9] +set_location_assignment PIN_AB17 -to GPIO_1[0] +set_location_assignment PIN_AG26 -to GPIO_1[10] +set_location_assignment PIN_AH24 -to GPIO_1[11] +set_location_assignment PIN_AH27 -to GPIO_1[12] +set_location_assignment PIN_AJ27 -to GPIO_1[13] +set_location_assignment PIN_AK29 -to GPIO_1[14] +set_location_assignment PIN_AK28 -to GPIO_1[15] +set_location_assignment PIN_AK27 -to GPIO_1[16] +set_location_assignment PIN_AJ26 -to GPIO_1[17] +set_location_assignment PIN_AK26 -to GPIO_1[18] +set_location_assignment PIN_AH25 -to GPIO_1[19] +set_location_assignment PIN_AA21 -to GPIO_1[1] +set_location_assignment PIN_AJ25 -to GPIO_1[20] +set_location_assignment PIN_AJ24 -to GPIO_1[21] +set_location_assignment PIN_AK24 -to GPIO_1[22] +set_location_assignment PIN_AG23 -to GPIO_1[23] +set_location_assignment PIN_AK23 -to GPIO_1[24] +set_location_assignment PIN_AH23 -to GPIO_1[25] +set_location_assignment PIN_AK22 -to GPIO_1[26] +set_location_assignment PIN_AJ22 -to GPIO_1[27] +set_location_assignment PIN_AH22 -to GPIO_1[28] +set_location_assignment PIN_AG22 -to GPIO_1[29] +set_location_assignment PIN_AB21 -to GPIO_1[2] +set_location_assignment PIN_AF24 -to GPIO_1[30] +set_location_assignment PIN_AF23 -to GPIO_1[31] +set_location_assignment PIN_AE22 -to GPIO_1[32] +set_location_assignment PIN_AD21 -to GPIO_1[33] +set_location_assignment PIN_AA20 -to GPIO_1[34] +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_location_assignment PIN_AC23 -to GPIO_1[3] +set_location_assignment PIN_AD24 -to GPIO_1[4] +set_location_assignment PIN_AE23 -to GPIO_1[5] +set_location_assignment PIN_AE24 -to GPIO_1[6] +set_location_assignment PIN_AF25 -to GPIO_1[7] +set_location_assignment PIN_AF26 -to GPIO_1[8] +set_location_assignment PIN_AG25 -to GPIO_1[9] +set_location_assignment PIN_AE26 -to HEX0[0] +set_location_assignment PIN_AE27 -to HEX0[1] +set_location_assignment PIN_AE28 -to HEX0[2] +set_location_assignment PIN_AG27 -to HEX0[3] +set_location_assignment PIN_AF28 -to HEX0[4] +set_location_assignment PIN_AG28 -to HEX0[5] +set_location_assignment PIN_AH28 -to HEX0[6] +set_location_assignment PIN_AJ29 -to HEX1[0] +set_location_assignment PIN_AH29 -to HEX1[1] +set_location_assignment PIN_AH30 -to HEX1[2] +set_location_assignment PIN_AG30 -to HEX1[3] +set_location_assignment PIN_AF29 -to HEX1[4] +set_location_assignment PIN_AF30 -to HEX1[5] +set_location_assignment PIN_AD27 -to HEX1[6] +set_location_assignment PIN_AB23 -to HEX2[0] +set_location_assignment PIN_AE29 -to HEX2[1] +set_location_assignment PIN_AD29 -to HEX2[2] +set_location_assignment PIN_AC28 -to HEX2[3] +set_location_assignment PIN_AD30 -to HEX2[4] +set_location_assignment PIN_AC29 -to HEX2[5] +set_location_assignment PIN_AC30 -to HEX2[6] +set_location_assignment PIN_AD26 -to HEX3[0] +set_location_assignment PIN_AC27 -to HEX3[1] +set_location_assignment PIN_AD25 -to HEX3[2] +set_location_assignment PIN_AC25 -to HEX3[3] +set_location_assignment PIN_AB28 -to HEX3[4] +set_location_assignment PIN_AB25 -to HEX3[5] +set_location_assignment PIN_AB22 -to HEX3[6] +set_location_assignment PIN_AA24 -to HEX4[0] +set_location_assignment PIN_Y23 -to HEX4[1] +set_location_assignment PIN_Y24 -to HEX4[2] +set_location_assignment PIN_W22 -to HEX4[3] +set_location_assignment PIN_W24 -to HEX4[4] +set_location_assignment PIN_V23 -to HEX4[5] +set_location_assignment PIN_W25 -to HEX4[6] +set_location_assignment PIN_V25 -to HEX5[0] +set_location_assignment PIN_AA28 -to HEX5[1] +set_location_assignment PIN_Y27 -to HEX5[2] +set_location_assignment PIN_AB27 -to HEX5[3] +set_location_assignment PIN_AB26 -to HEX5[4] +set_location_assignment PIN_AA26 -to HEX5[5] +set_location_assignment PIN_AA25 -to HEX5[6] +set_location_assignment PIN_AA30 -to IRDA_RXD +set_location_assignment PIN_AB30 -to IRDA_TXD +set_location_assignment PIN_AA14 -to KEY[0] +set_location_assignment PIN_AA15 -to KEY[1] +set_location_assignment PIN_W15 -to KEY[2] +set_location_assignment PIN_Y16 -to KEY[3] +set_location_assignment PIN_V16 -to LEDR[0] +set_location_assignment PIN_W16 -to LEDR[1] +set_location_assignment PIN_V17 -to LEDR[2] +set_location_assignment PIN_V18 -to LEDR[3] +set_location_assignment PIN_W17 -to LEDR[4] +set_location_assignment PIN_W19 -to LEDR[5] +set_location_assignment PIN_Y19 -to LEDR[6] +set_location_assignment PIN_W20 -to LEDR[7] +set_location_assignment PIN_W21 -to LEDR[8] +set_location_assignment PIN_Y21 -to LEDR[9] +set_location_assignment PIN_AD7 -to PS2_CLK +set_location_assignment PIN_AE7 -to PS2_DAT +set_location_assignment PIN_AD9 -to PS2_CLK2 +set_location_assignment PIN_AE9 -to PS2_DAT2 +set_location_assignment PIN_AB12 -to SW[0] +set_location_assignment PIN_AC12 -to SW[1] +set_location_assignment PIN_AF9 -to SW[2] +set_location_assignment PIN_AF10 -to SW[3] +set_location_assignment PIN_AD11 -to SW[4] +set_location_assignment PIN_AD12 -to SW[5] +set_location_assignment PIN_AE11 -to SW[6] +set_location_assignment PIN_AC9 -to SW[7] +set_location_assignment PIN_AD10 -to SW[8] +set_location_assignment PIN_AE12 -to SW[9] +set_location_assignment PIN_H15 -to TD_CLK27 +set_location_assignment PIN_D2 -to TD_DATA[0] +set_location_assignment PIN_B1 -to TD_DATA[1] +set_location_assignment PIN_E2 -to TD_DATA[2] +set_location_assignment PIN_B2 -to TD_DATA[3] +set_location_assignment PIN_D1 -to TD_DATA[4] +set_location_assignment PIN_E1 -to TD_DATA[5] +set_location_assignment PIN_C2 -to TD_DATA[6] +set_location_assignment PIN_B3 -to TD_DATA[7] +set_location_assignment PIN_A5 -to TD_HS +set_location_assignment PIN_F6 -to TD_RESET_N +set_location_assignment PIN_A3 -to TD_VS +set_location_assignment PIN_AF4 -to USB_B2_CLK +set_location_assignment PIN_AH4 -to USB_B2_DATA[0] +set_location_assignment PIN_AH3 -to USB_B2_DATA[1] +set_location_assignment PIN_AJ2 -to USB_B2_DATA[2] +set_location_assignment PIN_AJ1 -to USB_B2_DATA[3] +set_location_assignment PIN_AH2 -to USB_B2_DATA[4] +set_location_assignment PIN_AG3 -to USB_B2_DATA[5] +set_location_assignment PIN_AG2 -to USB_B2_DATA[6] +set_location_assignment PIN_AG1 -to USB_B2_DATA[7] +set_location_assignment PIN_AF5 -to USB_EMPTY +set_location_assignment PIN_AG5 -to USB_FULL +set_location_assignment PIN_AF6 -to USB_OE_N +set_location_assignment PIN_AG6 -to USB_RD_N +set_location_assignment PIN_AG7 -to USB_RESET_N +set_location_assignment PIN_AG8 -to USB_SCL +set_location_assignment PIN_AF8 -to USB_SDA +set_location_assignment PIN_AH5 -to USB_WR_N +set_location_assignment PIN_B13 -to VGA_B[0] +set_location_assignment PIN_G13 -to VGA_B[1] +set_location_assignment PIN_H13 -to VGA_B[2] +set_location_assignment PIN_F14 -to VGA_B[3] +set_location_assignment PIN_H14 -to VGA_B[4] +set_location_assignment PIN_F15 -to VGA_B[5] +set_location_assignment PIN_G15 -to VGA_B[6] +set_location_assignment PIN_J14 -to VGA_B[7] +set_location_assignment PIN_F10 -to VGA_BLANK_N +set_location_assignment PIN_A11 -to VGA_CLK +set_location_assignment PIN_J9 -to VGA_G[0] +set_location_assignment PIN_J10 -to VGA_G[1] +set_location_assignment PIN_H12 -to VGA_G[2] +set_location_assignment PIN_G10 -to VGA_G[3] +set_location_assignment PIN_G11 -to VGA_G[4] +set_location_assignment PIN_G12 -to VGA_G[5] +set_location_assignment PIN_F11 -to VGA_G[6] +set_location_assignment PIN_E11 -to VGA_G[7] +set_location_assignment PIN_B11 -to VGA_HS +set_location_assignment PIN_A13 -to VGA_R[0] +set_location_assignment PIN_C13 -to VGA_R[1] +set_location_assignment PIN_E13 -to VGA_R[2] +set_location_assignment PIN_B12 -to VGA_R[3] +set_location_assignment PIN_C12 -to VGA_R[4] +set_location_assignment PIN_D12 -to VGA_R[5] +set_location_assignment PIN_E12 -to VGA_R[6] +set_location_assignment PIN_F13 -to VGA_R[7] +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_D11 -to VGA_VS +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/task4/task4.sv b/task4/task4.sv index 1e2514f..231c4b1 100644 --- a/task4/task4.sv +++ b/task4/task4.sv @@ -1,61 +1,52 @@ -// This module contains a Verilog description of the top level module -// Assuming you don't modify the inputs and outputs of the various submodules, -// you should not have to modify anything in this file. +module task4(CLOCK_50, KEY, LEDR, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0); -module task4(input logic CLOCK_50, input logic [3:0] KEY, output logic [9:0] LEDR, - output logic [6:0] HEX5, output logic [6:0] HEX4, output logic [6:0] HEX3, - output logic [6:0] HEX2, output logic [6:0] HEX1, output logic [6:0] HEX0); + input logic CLOCK_50; + input logic [3:0] KEY; + output logic [9:0] LEDR; + output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5; -// some local signals + logic fast_clock, slow_clock, resetb, + load_pcard1, load_pcard2, load_pcard3, + load_dcard1, load_dcard2, load_dcard3; + logic [3:0] pscore, dscore, pcard3; -logic fast_clock, slow_clock, resetb; -logic load_pcard1, load_pcard2, load_pcard3; -logic load_dcard1, load_dcard2, load_dcard3; -logic [3:0] pscore, dscore; -logic [3:0] pcard3; - -assign resetb = KEY[3]; -assign slow_clock = KEY[0]; -assign fast_clock = CLOCK_50; + assign resetb = KEY[3]; + assign slow_clock = KEY[0]; + assign fast_clock = CLOCK_50; -// instantiate the datapath - -datapath dp(.slow_clock(slow_clock), - .fast_clock(fast_clock), - .resetb(resetb), - .load_pcard1(load_pcard1), - .load_pcard2(load_pcard2), - .load_pcard3(load_pcard3), - .load_dcard1(load_dcard1), - .load_dcard2(load_dcard2), - .load_dcard3(load_dcard3), - .dscore_out(dscore), - .pscore_out(pscore), - .pcard3_out(pcard3), - .HEX5(HEX5), - .HEX4(HEX4), - .HEX3(HEX3), - .HEX2(HEX2), - .HEX1(HEX1), - .HEX0(HEX0)); - -assign LEDR[3:0] = pscore; -assign LEDR[7:4] = dscore; + datapath dp(.slow_clock(slow_clock), + .fast_clock(fast_clock), + .resetb(resetb), + .load_pcard1(load_pcard1), + .load_pcard2(load_pcard2), + .load_pcard3(load_pcard3), + .load_dcard1(load_dcard1), + .load_dcard2(load_dcard2), + .load_dcard3(load_dcard3), + .dscore_out(dscore), + .pscore_out(pscore), + .pcard3_out(pcard3), + .HEX5(HEX5), + .HEX4(HEX4), + .HEX3(HEX3), + .HEX2(HEX2), + .HEX1(HEX1), + .HEX0(HEX0)); -// instantiate the state machine + assign LEDR[3:0] = pscore; + assign LEDR[7:4] = dscore; -statemachine sm(.slow_clock(slow_clock), - .resetb(resetb), - .dscore(dscore), - .pscore(pscore), - .pcard3(pcard3), - .load_pcard1(load_pcard1), - .load_pcard2(load_pcard2), - .load_pcard3(load_pcard3), - .load_dcard1(load_dcard1), - .load_dcard2(load_dcard2), - .load_dcard3(load_dcard3), - .player_win_light(LEDR[8]), - .dealer_win_light(LEDR[9])); - -endmodule + statemachine sm(.slow_clock(slow_clock), + .resetb(resetb), + .dscore(dscore), + .pscore(pscore), + .pcard3(pcard3), + .load_pcard1(load_pcard1), + .load_pcard2(load_pcard2), + .load_pcard3(load_pcard3), + .load_dcard1(load_dcard1), + .load_dcard2(load_dcard2), + .load_dcard3(load_dcard3), + .player_win_light(LEDR[8]), + .dealer_win_light(LEDR[9])); +endmodule: task4 -- cgit v1.2.3